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Searched refs:ExtTy (Results 1 – 25 of 26) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTypePromotion.cpp115 IntegerType *ExtTy = nullptr; member in __anon7086da680111::IRPromoter
136 ExtTy = IntegerType::get(Ctx, PromotedWidth); in IRPromoter()
138 ExtTy->getPrimitiveSizeInBits().getFixedSize() && in IRPromoter()
484 assert(V->getType() != ExtTy && "zext already extends to i32"); in ExtendSources()
490 Value *ZExt = Builder.CreateZExt(V, ExtTy); in ExtendSources()
535 if ((Op->getType() == ExtTy) || !isa<IntegerType>(Op->getType())) in PromoteTree()
539 Constant *NewConst = ConstantExpr::getZExt(Const, ExtTy); in PromoteTree()
542 I->setOperand(i, UndefValue::get(ExtTy)); in PromoteTree()
547 I->mutateType(ExtTy); in PromoteTree()
622 if (ZExt->getDestTy() != ExtTy) in Cleanup()
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H A DCodeGenPrepare.cpp4024 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in addPromotedInst() local
4029 if (It->second.getInt() == ExtTy) in addPromotedInst()
4035 ExtTy = BothExtension; in addPromotedInst()
4037 PromotedInsts[ExtOpnd] = TypeIsSExt(ExtOpnd->getType(), ExtTy); in addPromotedInst()
4047 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in getOrigType() local
4049 if (It != PromotedInsts.end() && It->second.getInt() == ExtTy) in getOrigType()
4259 Type *ExtTy = Ext->getType(); in getAction() local
4264 if (!ExtOpnd || !canGetThrough(ExtOpnd, ExtTy, PromotedInsts, IsSExt)) in getAction()
4281 if (!ExtOpnd->hasOneUse() && !TLI.isTruncateFree(ExtTy, ExtOpnd->getType())) in getAction()
5642 Type *ExtTy = FirstUser->getType(); in hasSameExtUse() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1731 Type *ExtTy = RetTy->getWithNewBitWidth(ExtSize); in getTypeBasedIntrinsicInstrCost() local
1738 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
1740 thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind); in getTypeBasedIntrinsicInstrCost()
1741 Cost += 2 * thisT()->getCastInstrCost(Instruction::Trunc, RetTy, ExtTy, in getTypeBasedIntrinsicInstrCost()
1800 Type *ExtTy = MulTy->getWithNewBitWidth(ExtSize); in getTypeBasedIntrinsicInstrCost() local
1807 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
1809 thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind); in getTypeBasedIntrinsicInstrCost()
1810 Cost += 2 * thisT()->getCastInstrCost(Instruction::Trunc, MulTy, ExtTy, in getTypeBasedIntrinsicInstrCost()
2137 VectorType *ExtTy = VectorType::get(ResTy, Ty); in getExtendedAddReductionCost() local
2139 Instruction::Add, ExtTy, false, CostKind); in getExtendedAddReductionCost()
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H A DSelectionDAGNodes.h533 uint16_t ExtTy : 2; // enum ISD::LoadExtType
2258 LoadSDNodeBits.ExtTy = ETy;
2267 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2360 LoadSDNodeBits.ExtTy = ETy;
2365 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2471 LoadSDNodeBits.ExtTy = ETy;
2477 return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
H A DSelectionDAG.h1318 ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy);
H A DTargetLowering.h1526 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.h128 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp586 MVT ExtTy = ty(ExtVec); in buildHvxVectorReg() local
587 unsigned ExtLen = ExtTy.getVectorNumElements(); in buildHvxVectorReg()
612 SDValue S = DAG.getVectorShuffle(ExtTy, dl, ExtVec, in buildHvxVectorReg()
613 DAG.getUNDEF(ExtTy), Mask); in buildHvxVectorReg()
1495 MVT ExtTy = typeExtElem(ResTy, 2); in LowerHvxMulh() local
1499 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
H A DHexagonISelLowering.h322 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DHexagonISelLowering.cpp3538 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth() argument
3540 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp325 LLT ExtTy = getLLTForType(*RetInfo.Ty, DL); in lowerReturnVal() local
326 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
H A DAMDGPUISelLowering.cpp721 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
724 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h1278 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DX86InstrSSE.td4970 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
4994 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5002 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5004 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5007 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5009 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5012 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5049 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5070 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5074 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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H A DX86InstrAVX512.td9419 SDNode OpNode, SDNode InVecNode, string ExtTy,
9420 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9438 SDNode OpNode, SDNode InVecNode, string ExtTy,
9439 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9457 SDNode OpNode, SDNode InVecNode, string ExtTy,
9458 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9476 SDNode OpNode, SDNode InVecNode, string ExtTy,
9477 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
9495 SDNode OpNode, SDNode InVecNode, string ExtTy,
9496 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h568 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DAArch64ISelLowering.cpp3500 const EVT &ExtTy, in addRequiredExtensionForVectorMULL() argument
3505 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
4236 ISD::LoadExtType ExtTy = MGT->getExtensionType(); in LowerMGATHER() local
4246 bool ResNeedsSignExtend = ExtTy == ISD::EXTLOAD || ExtTy == ISD::SEXTLOAD; in LowerMGATHER()
10942 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
10945 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
10950 if (ExtTy != ISD::NON_EXTLOAD) in shouldReduceLoadWidth()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DScalarEvolution.cpp3153 IntegerType *ExtTy = in getUDivExpr() local
3162 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3163 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3164 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3176 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3177 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3178 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3206 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
3207 if (getZeroExtendExpr(M, ExtTy) == getMulExpr(Operands)) in getUDivExpr()
3238 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/
H A DAutoUpgrade.cpp1939 Type *ExtTy = Type::getInt32Ty(C); in UpgradeIntrinsicCall() local
1941 ExtTy = Type::getInt64Ty(C); in UpgradeIntrinsicCall()
1943 ExtTy->getPrimitiveSizeInBits(); in UpgradeIntrinsicCall()
1944 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); in UpgradeIntrinsicCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1883 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateReg() argument
1891 Op->Reg.ShiftExtend.Type = ExtTy; in CreateReg()
1902 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateVectorReg() argument
1908 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp4725 const TypeSetByHwMode &ExtTy = Dst->getExtType(I); in importExplicitDefRenderers() local
4726 if (!ExtTy.isMachineValueType()) in importExplicitDefRenderers()
4729 auto OpTy = MVTToLLT(ExtTy.getMachineValueType().SimpleTy); in importExplicitDefRenderers()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7541 ISD::LoadExtType ExtTy, bool isExpanding) { in getMaskedLoad() argument
7552 dl.getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO)); in getMaskedLoad()
7560 AM, ExtTy, isExpanding, MemVT, MMO); in getMaskedLoad()
7633 ISD::LoadExtType ExtTy) { in getMaskedGather() argument
7640 dl.getIROrder(), VTs, VT, MMO, IndexType, ExtTy)); in getMaskedGather()
7650 VTs, VT, MMO, IndexType, ExtTy); in getMaskedGather()
H A DDAGCombiner.cpp18401 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad() local
18403 if (!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT)) in scalarizeExtractedVectorLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp3720 LLT ExtTy = MRI.getType(DstReg); in applyExtendThroughPhis() local
3740 auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy, in applyExtendThroughPhis()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8867 const EVT &ExtTy, in AddRequiredExtensionForVMULL() argument
8872 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()

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