| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 389 bool isRegOffOpcode(unsigned ExtOpc) const ;
390 unsigned getRegOffOpcode(unsigned ExtOpc) const;
391 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
864 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
868 switch (ExtOpc) { in getRegOffOpcode()
873 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
881 switch (ExtOpc) { in getRegOffOpcode()
954 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
955 return ExtOpc; in getRegOffOpcode()
964 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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| H A D | HexagonBitSimplify.cpp | 2517 unsigned ExtOpc = 0; in simplifyExtractLow() local
2520 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2522 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2524 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2526 if (ExtOpc == 0) { in simplifyExtractLow()
2527 ExtOpc = in simplifyExtractLow()
2539 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2543 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2555 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2557 switch (ExtOpc) { in simplifyExtractLow()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 450 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
453 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
454 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
464 Opcode = ExtOpc; in buildExtOrTrunc()
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| H A D | LegalizerHelper.cpp | 2155 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2157 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2158 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2161 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1690 unsigned ExtOpc = in lowerScalarSplat() local
1692 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
3280 unsigned ExtOpc = in lowerVectorIntrinsicSplats() local
3282 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicSplats()
4596 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
4599 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
4600 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
4763 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
4765 ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND in ReplaceNodeResults()
4768 Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1876 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1879 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1881 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1893 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 712 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1233 unsigned ExtOpc = in PromoteOperand() local
1235 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
10336 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
10350 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
10352 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
10674 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
10685 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
10695 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
10714 ISD::NodeType ExtOpc) { in tryToFoldExtOfMaskedLoad() argument
10729 SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); in tryToFoldExtOfMaskedLoad()
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| H A D | TargetLowering.cpp | 4528 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
4531 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20800 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
20807 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
20808 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
24025 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
24028 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
28502 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift() local
28503 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
43285 unsigned ExtOpc = LHS.getOpcode(); in combineShiftToPMULH() local
43286 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combineShiftToPMULH()
43287 RHS.getOpcode() != ExtOpc) in combineShiftToPMULH()
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