Searched refs:DispatchWidth (Results 1 – 10 of 10) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 32 : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), in DispatchStage()
34 if (!DispatchWidth) in DispatchStage()
35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
83 if (NumMicroOps > DispatchWidth) { in dispatch()
84 assert(AvailableEntries == DispatchWidth); in dispatch()
86 CarryOver = NumMicroOps - DispatchWidth; in dispatch()
131 std::min(DispatchWidth, NumMicroOps)); in dispatch()
139 AvailableEntries = DispatchWidth; in cycleStart()
143 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver; in cycleStart()
144 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries; in cycleStart()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| H A D | SummaryView.cpp | 27 : SM(Model), Source(S), DispatchWidth(Width?Width: Model.IssueWidth), in SummaryView()
75 TempStream << "\nDispatch Width: " << DV.DispatchWidth; in printView()
92 DV.DispatchWidth = DispatchWidth; in collectData()
96 DV.BlockRThroughput = computeBlockRThroughput(SM, DispatchWidth, NumMicroOps, in collectData()
107 {"DispatchWidth", DV.DispatchWidth}, in toJSON()
|
| H A D | SummaryView.h | 43 const unsigned DispatchWidth; variable
54 unsigned DispatchWidth; member
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Context.h | 37 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), in MicroOpQueueSize()
42 unsigned DispatchWidth; member
|
| H A D | Support.h | 108 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | Support.cpp | 82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput() argument
88 double Max = static_cast<double>(NumMicroOps) / DispatchWidth; in computeBlockRThroughput()
|
| H A D | Context.cpp | 47 auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, in createDefaultPipeline()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| H A D | DispatchStage.h | 50 unsigned DispatchWidth; variable
|
| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/ |
| H A D | llvm-mca.cpp | 118 DispatchWidth("dispatch", cl::desc("Override the processor dispatch width"), variable
468 mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth, in main()
563 std::make_unique<mca::SummaryView>(SM, Insts, DispatchWidth)); in main()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/docs/CommandGuide/ |
| H A D | llvm-mca.rst | 391 Field *DispatchWidth* is the maximum number of micro opcodes that are dispatched
393 in-order backend, *DispatchWidth* is the maximum number of micro opcodes issued
|