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Searched refs:DestVT (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
998 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPExt() local
1000 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1077 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPTrunc() local
1079 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp168 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
958 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPExt() local
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
976 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPTrunc() local
978 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1268 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1272 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1440 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1442 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1444 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
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H A DPPCISelLowering.h971 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp8860 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8861 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
8862 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8870 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8871 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
8872 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
8880 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
8881 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
8882 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
16122 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp233 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
234 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction()
235 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
247 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
248 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
249 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp231 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
232 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2804 MVT DestVT; in selectFPToInt() local
2805 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2819 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2821 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2824 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2826 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2829 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2837 MVT DestVT; in selectIntToFP() local
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H A DAArch64ISelLowering.cpp8282 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
8289 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8309 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8315 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8320 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8323 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8334 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
16361 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in PerformDAGCombine() local
16364 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds); in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFastISel.cpp201 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1734 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1738 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1949 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1950 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
1952 ArgVT = DestVT; in ProcessCallArgs()
1958 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1959 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
1961 ArgVT = DestVT; in ProcessCallArgs()
2036 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
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H A DARMISelLowering.cpp7810 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
7818 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7834 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7840 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7845 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7848 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7851 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
876 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
877 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
903 EVT IDestVT = DestVT.changeTypeToInteger(); in LegalizeLoadOps()
908 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result); in LegalizeLoadOps()
1689 EVT DestVT, const SDLoc &dl) { in EmitStackConvert() argument
1690 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); in EmitStackConvert()
1694 EVT DestVT, const SDLoc &dl, in EmitStackConvert() argument
1698 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert()
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H A DLegalizeTypes.cpp887 EVT DestVT) { in CreateStackStoreLoad() argument
894 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad()
903 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
H A DSelectionDAGBuilder.cpp3207 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitICmp() local
3209 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
3230 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitFCmp() local
3232 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
3383 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitTrunc() local
3385 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
3392 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitZExt() local
3394 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
3401 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitSExt() local
3403 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitSExt()
[all …]
H A DLegalizeVectorTypes.cpp373 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
391 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp()
1938 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
1940 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
1956 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
H A DLegalizeTypes.h220 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp919 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
926 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2510 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2515 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
2521 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
2526 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
2537 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
2540 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
2546 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local
2552 if (DestVT == MVT::f16) in LowerSINT_TO_FP()
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H A DSIISelLowering.h253 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp867 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
870 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1115 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1116 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1117 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1118 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT()
1579 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1580 RegisterVT = DestVT; in getVectorTypeBreakdown()
1582 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1587 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2248 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2249 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2254 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2256 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2659 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2660 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2669 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2670 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2672 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19785 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
19795 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
19815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
24059 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
24061 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
24065 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
24074 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
24077 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()