Searched refs:DesiredReg (Results 1 – 3 of 3) sorted by relevance
1593 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP() local1601 assert(ARM::tGPRRegClass.contains(DesiredReg) && in ExpandCMP_SWAP()1616 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) in ExpandCMP_SWAP()1617 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()1638 .addReg(DesiredReg) in ExpandCMP_SWAP()1721 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP_64() local1727 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()1728 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
197 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP() local221 .addReg(DesiredReg) in expandCMP_SWAP()
4983 const unsigned DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg() local4997 .addUse(DesiredReg) in selectAtomicCmpXchg()5003 .addUse(DesiredReg) in selectAtomicCmpXchg()