| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 167 const MachineOperand *DefMO = nullptr; in runOnMachineFunction() local
188 if (DefMO) { in runOnMachineFunction()
192 DefMO = &MO; in runOnMachineFunction()
193 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
194 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
219 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
|
| H A D | FixupStatepointCallerSaved.cpp | 484 MachineOperand &DefMO = MI.getOperand(I); in rewriteStatepoint() local
485 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand"); in rewriteStatepoint()
486 Register Reg = DefMO.getReg(); in rewriteStatepoint()
487 assert(DefMO.isTied() && "Def is expected to be tied"); in rewriteStatepoint()
|
| H A D | MachineLICM.cpp | 1073 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1074 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1077 Register Reg = DefMO.getReg(); in IsCheapInstruction()
|
| H A D | ModuloSchedule.cpp | 1603 for (MachineOperand &DefMO : MI->defs()) { in filterInstructions()
1605 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in filterInstructions()
1614 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in filterInstructions()
1917 for (MachineOperand &DefMO : MI->defs()) { in rewriteUsesOf()
1919 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in rewriteUsesOf()
1928 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in rewriteUsesOf()
|
| H A D | MachineInstr.cpp | 1100 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1102 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1104 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1120 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
|
| H A D | RegisterCoalescer.cpp | 1347 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1348 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1357 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1358 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TileShapeInfo.h | 73 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { in deduceImm() local
74 const auto *MI = DefMO.getParent(); in deduceImm()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 199 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
200 if (!DefMO.isReg()) in findStartOfTree()
202 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
|
| H A D | WebAssemblyRegStackify.cpp | 642 MachineOperand &DefMO = Def->getOperand(0); in moveAndTeeForMultiUse() local
646 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
648 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 295 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
296 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
297 return &DefMO; in findSingleRegDef()
|
| H A D | SIInsertWaitcnts.cpp | 605 MachineOperand &DefMO = Inst.getOperand(I); in updateByEvent() local
606 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
607 TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()
609 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)), in updateByEvent()
|
| H A D | SIInstrInfo.h | 771 const MachineOperand &DefMO) const { in isInlineConstant() argument
778 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4228 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4230 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) { in getOperandLatency()
4231 if (DefMO.isImplicit()) { in getOperandLatency()
4232 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 446 const MachineOperand &DefMO, unsigned Reg,
|
| H A D | ARMBaseInstrInfo.cpp | 4339 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4340 Register Reg = DefMO.getReg(); in getOperandLatency()
4362 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4369 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4397 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 176 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
177 Register Reg = DefMO.getReg(); in getOperandLatency()
|