Searched refs:Def1 (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 110 MachineInstr *Def1, *Def2; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
304 MachineInstr &Def1 = *It1, &Def2 = *It2; in genMuxInBlock() local
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock()
327 MachineBasicBlock::iterator At = CanDown ? Def2 : Def1; in genMuxInBlock()
328 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)); in genMuxInBlock()
338 if (!MX.At->getParent() || !MX.Def1->getParent() || !MX.Def2->getParent()) in genMuxInBlock()
348 B.remove(MX.Def1); in genMuxInBlock()
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| H A D | HexagonEarlyIfConv.cpp | 480 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); in computePhiCost() local
482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) in computePhiCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCReduceCRLogicals.cpp | 472 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(), in createCRLogicalOpInfo() local
474 assert(Def1 && "Must be able to find a definition of operand 1."); in createCRLogicalOpInfo()
476 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg()); in createCRLogicalOpInfo()
489 Ret.TrueDefs = std::make_pair(Def1, Def2); in createCRLogicalOpInfo()
491 Ret.TrueDefs = std::make_pair(Def1, nullptr); in createCRLogicalOpInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1896 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue() local
1899 if (!produceSameValue(*Def0, *Def1, MRI)) in produceSameValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5116 bool Def1 = !Elems[I1].isUndef(); in buildVector() local
5118 if (Def1 || Def2) { in buildVector()
5119 SDValue Elem1 = Elems[Def1 ? I1 : I2]; in buildVector()
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