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Searched refs:Def (Results 1 – 25 of 237) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/TableGen/
H A DDirectiveEmitter.h16 Def = DirectiveLanguages[0]; in DirectiveLanguage()
19 StringRef getName() const { return Def->getValueAsString("name"); } in getName()
22 return Def->getValueAsString("cppNamespace"); in getCppNamespace()
26 return Def->getValueAsString("directivePrefix"); in getDirectivePrefix()
30 return Def->getValueAsString("clausePrefix"); in getClausePrefix()
34 return Def->getValueAsString("clauseEnumSetClass"); in getClauseEnumSetClass()
38 return Def->getValueAsString("flangClauseBaseClass"); in getFlangClauseBaseClass()
42 return Def->getValueAsBit("makeEnumAvailableInNamespace"); in hasMakeEnumAvailableInNamespace()
46 return Def->getValueAsBit("enableBitmaskEnumInNamespace"); in hasEnableBitmaskEnumInNamespace()
60 const llvm::Record *Def;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp77 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction() local
78 switch (Def->getOpcode()) { in runOnMachineFunction()
81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
101 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
105 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
109 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
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H A DWebAssemblyRegStackify.cpp258 static bool shouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, in shouldRematerialize() argument
260 return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def, &AA); in shouldRematerialize()
270 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) in getVRegDef() local
271 return Def; in getVRegDef()
284 static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, in hasOneUse() argument
293 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot()); in hasOneUse()
313 static bool isSafeToMove(const MachineOperand *Def, const MachineOperand *Use, in isSafeToMove() argument
317 const MachineInstr *DefI = Def->getParent(); in isSafeToMove()
333 if (Def != DefI->defs().begin()) in isSafeToMove()
514 MachineInstr *Def, MachineBasicBlock &MBB, in moveForSingleUse() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp258 RegSubRegPair Def, RewriteMapTy &RewriteMap);
370 const MachineInstr *Def = nullptr; member in __anonbcd030b40111::ValueTracker
426 Def = MRI.getVRegDef(Reg); in ValueTracker()
1118 RegSubRegPair Def, in getNewSource() argument
1121 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1229 RegSubRegPair Def, RewriteMapTy &RewriteMap) { in rewriteSource() argument
1230 assert(!Register::isPhysicalRegister(Def.Reg) && in rewriteSource()
1234 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); in rewriteSource()
1237 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1245 if (Def.SubReg) { in rewriteSource()
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H A DReachingDefAnalysis.cpp163 int Def = Incoming[Unit]; in reprocessBasicBlock() local
164 if (Def == ReachingDefDefaultVal) in reprocessBasicBlock()
169 if (*Start >= Def) in reprocessBasicBlock()
173 *Start = Def; in reprocessBasicBlock()
176 MBBReachingDefs[MBBNumber][Unit].insert(Start, Def); in reprocessBasicBlock()
181 if (MBBOutRegsInfos[MBBNumber][Unit] < Def - NumInsts) in reprocessBasicBlock()
182 MBBOutRegsInfos[MBBNumber][Unit] = Def - NumInsts; in reprocessBasicBlock()
248 for (int Def : RegUnitDefs) { in traverse() local
249 assert(Def > LastDef && "Defs must be sorted and unique"); in traverse()
250 LastDef = Def; in traverse()
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H A DMachineCopyPropagation.cpp157 MCRegister Def = MI->getOperand(0).getReg().asMCReg(); in trackCopy() local
161 for (MCRegUnitIterator RUI(Def, &TRI); RUI.isValid(); ++RUI) in trackCopy()
169 if (!is_contained(Copy.DefRegs, Def)) in trackCopy()
170 Copy.DefRegs.push_back(Def); in trackCopy()
281 bool eraseIfRedundant(MachineInstr &Copy, MCRegister Src, MCRegister Def);
291 const MachineOperand &MODef, Register Def);
337 MCRegister Def, const TargetRegisterInfo *TRI) { in isNopCopy() argument
340 if (Src == PreviousSrc && Def == PreviousDef) in isNopCopy()
345 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
352 MCRegister Src, MCRegister Def) { in eraseIfRedundant() argument
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H A DDetectDeadLanes.cpp88 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
249 const MachineOperand &Def = MI.getOperand(0); in transferUsedLanes() local
250 Register DefReg = Def.getReg(); in transferUsedLanes()
284 const MachineOperand &Def = *MI.defs().begin(); in transferDefinedLanesStep() local
285 Register DefReg = Def.getReg(); in transferDefinedLanesStep()
295 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
307 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def, in transferDefinedLanes() argument
309 const MachineInstr &MI = *Def.getParent(); in transferDefinedLanes()
343 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
345 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg()); in transferDefinedLanes()
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H A DModuloSchedule.cpp385 Register Def = BBI->getOperand(0).getReg(); in generateExistingPhis() local
400 unsigned NumStages = getStagesForReg(Def, CurStageNum); in generateExistingPhis()
405 rewriteScheduledInstr(NewBB, InstrMap, CurStageNum, 0, &*BBI, Def, in generateExistingPhis()
408 VRMap[CurStageNum][Def] = VRMap[CurStageNum][LoopVal]; in generateExistingPhis()
494 VRMap[PrevStage - np + 1].count(Def)) in generateExistingPhis()
495 PhiOp2 = VRMap[PrevStage - np + 1][Def]; in generateExistingPhis()
502 else if (VRMap[PrevStage - np].count(Def) && in generateExistingPhis()
505 PhiOp2 = VRMap[PrevStage - np][Def]; in generateExistingPhis()
529 Def, NewReg); in generateExistingPhis()
531 VRMap[CurStageNum - np][Def] = NewReg; in generateExistingPhis()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/WindowsManifest/
H A DWindowsManifestMerger.cpp127 for (xmlNsPtr Def = Node->nsDef; Def; Def = Def->next) { in search() local
128 if (Def->prefix && xmlStringsEqual(Def->href, HRef)) { in search()
129 return Def; in search()
155 if (xmlNsPtr Def = search(HRef, Node)) in searchOrDefine() local
156 return Def; in searchOrDefine()
157 if (xmlNsPtr Def = xmlNewNs(Node, HRef, getPrefixForHref(HRef))) in searchOrDefine() local
158 return Def; in searchOrDefine()
182 for (xmlNsPtr Def = Node->nsDef; Def; Def = Def->next) { in getNamespaceWithPrefix() local
183 if (xmlStringsEqual(Def->prefix, Prefix)) { in getNamespaceWithPrefix()
184 return Def; in getNamespaceWithPrefix()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DExegesisEmitter.cpp52 void emitPfmCountersInfo(const Record &Def,
74 for (Record *Def : Records.getAllDerivedDefinitions("ProcPfmCounters")) { in collectPfmCounters()
78 Def->getValueAsListOfDefs("IssueCounters")) { in collectPfmCounters()
88 AddPfmCounterName(Def->getValueAsDef("CycleCounter")); in collectPfmCounters()
89 AddPfmCounterName(Def->getValueAsDef("UopsCounter")); in collectPfmCounters()
107 void ExegesisEmitter::emitPfmCountersInfo(const Record &Def, in emitPfmCountersInfo() argument
111 Def.getValueAsDef("CycleCounter")->getValueAsString("Counter"); in emitPfmCountersInfo()
113 Def.getValueAsDef("UopsCounter")->getValueAsString("Counter"); in emitPfmCountersInfo()
115 Def.getValueAsListOfDefs("IssueCounters").size(); in emitPfmCountersInfo()
117 OS << "\nstatic const PfmCountersInfo " << Target << Def.getName() in emitPfmCountersInfo()
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H A DCodeGenSchedule.h61 CodeGenSchedRW(unsigned Idx, Record *Def) in CodeGenSchedRW()
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
63 Name = std::string(Def->getName()); in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
67 IsVariadic = Def->getValueAsBit("Variadic"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
393 void addDefinition(const Record *Def) { Definitions.push_back(Def); } in addDefinition() argument
525 CodeGenSchedRW &getSchedRW(Record *Def) { in getSchedRW() argument
526 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelUtils.cpp18 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); in getBaseWithConstantOffset() local
19 if (!Def) in getBaseWithConstantOffset()
22 if (Def->getOpcode() == TargetOpcode::G_CONSTANT) { in getBaseWithConstantOffset()
24 const MachineOperand &Op = Def->getOperand(1); in getBaseWithConstantOffset()
34 if (Def->getOpcode() == TargetOpcode::G_ADD) { in getBaseWithConstantOffset()
36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset))) in getBaseWithConstantOffset()
37 return std::make_pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset)))) in getBaseWithConstantOffset()
41 return std::make_pair(Def->getOperand(1).getReg(), Offset); in getBaseWithConstantOffset()
45 if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) { in getBaseWithConstantOffset()
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H A DSIFoldOperands.cpp500 MachineInstr *Def = MRI.getVRegDef(UseReg); in getRegSeqInit() local
501 if (!Def || !Def->isRegSequence()) in getRegSeqInit()
504 for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) { in getRegSeqInit()
505 MachineOperand *Sub = &Def->getOperand(I); in getRegSeqInit()
523 Defs.emplace_back(Sub, Def->getOperand(I + 1).getImm()); in getRegSeqInit()
565 MachineInstr *Def = MRI.getVRegDef(UseReg); in tryToFoldACImm() local
567 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
568 MachineOperand &DefOp = Def->getOperand(1); in tryToFoldACImm()
769 MachineOperand *Def = Defs[I].first; in foldOperand() local
771 if (Def->isImm() && in foldOperand()
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/netbsd-src/external/apache2/llvm/dist/clang/lib/Format/
H A DMacroExpander.cpp61 Def.Name = Current->TokenText; in parse()
64 Def.ObjectLike = false; in parse()
71 return Def; in parse()
79 Def.Params.push_back(Current); in parseParams()
80 Def.ArgMap[Def.Params.back()->TokenText] = Def.Params.size() - 1; in parseParams()
103 Def.Body.push_back(Current); in parseTail()
106 Def.Body.push_back(Current); in parseTail()
118 Definition Def; member in clang::format::MacroExpander::DefinitionParser
162 const Definition &Def = Definitions.find(ID->TokenText)->second; in expand() local
181 auto I = Def.ArgMap.find(Tok->TokenText); in expand()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/
H A DDominators.cpp130 const Instruction *Def = dyn_cast<Instruction>(DefV); in dominates() local
131 if (!Def) { in dominates()
138 const BasicBlock *DefBB = Def->getParent(); in dominates()
149 if (Def == User) in dominates()
156 if (isa<InvokeInst>(Def) || isa<CallBrInst>(Def) || isa<PHINode>(User)) in dominates()
157 return dominates(Def, UseBB); in dominates()
162 return Def->comesBefore(User); in dominates()
167 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
169 const BasicBlock *DefBB = Def->getParent(); in dominates()
184 if (const auto *II = dyn_cast<InvokeInst>(Def)) { in dominates()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp209 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
211 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
222 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
224 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
302 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
304 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
315 Def->eraseFromParent(); in transformInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/ToolDrivers/llvm-dlltool/
H A DDlltoolDriver.cpp131 Expected<COFFModuleDefinition> Def = in dlltoolDriverMain() local
134 if (!Def) { in dlltoolDriverMain()
136 << errorToErrorCode(Def.takeError()).message(); in dlltoolDriverMain()
142 Def->OutputFile = Arg->getValue(); in dlltoolDriverMain()
144 if (Def->OutputFile.empty()) { in dlltoolDriverMain()
156 for (COFFShortExport& E : Def->Exports) { in dlltoolDriverMain()
164 for (COFFShortExport& E : Def->Exports) { in dlltoolDriverMain()
181 writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine, true)) in dlltoolDriverMain()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DPredicateInfo.cpp104 Value *Def = nullptr; member
149 bool isADef = A.Def; in operator ()()
150 bool isBDef = B.Def; in operator ()()
159 if (!VD.Def && VD.U) { in getBlockEdge()
192 bool isADef = A.Def; in comparePHIRelated()
193 bool isBDef = B.Def; in comparePHIRelated()
194 assert((!A.Def || !A.U) && (!B.Def || !B.U) && in comparePHIRelated()
202 if (VD.Def) in getMiddleDef()
203 return VD.Def; in getMiddleDef()
222 const Instruction *getDefOrUser(const Value *Def, const Use *U) const { in getDefOrUser()
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H A DUnifyLoopExits.cpp113 auto Def = II.first; in INITIALIZE_PASS_DEPENDENCY() local
114 LLVM_DEBUG(dbgs() << "externally used: " << Def->getName() << "\n"); in INITIALIZE_PASS_DEPENDENCY()
115 auto NewPhi = PHINode::Create(Def->getType(), Incoming.size(), in INITIALIZE_PASS_DEPENDENCY()
116 Def->getName() + ".moved", in INITIALIZE_PASS_DEPENDENCY()
120 if (Def->getParent() == In || DT.dominates(Def, In)) { in INITIALIZE_PASS_DEPENDENCY()
122 NewPhi->addIncoming(Def, In); in INITIALIZE_PASS_DEPENDENCY()
125 NewPhi->addIncoming(UndefValue::get(Def->getType()), In); in INITIALIZE_PASS_DEPENDENCY()
132 U->replaceUsesOfWith(Def, NewPhi); in INITIALIZE_PASS_DEPENDENCY()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DInstruction.cpp189 if (!all_of(getDefs(), [](const WriteState &Def) { return Def.isReady(); })) in updatePending() argument
206 [](const WriteState &Def) { return !Def.getDependentWrite(); })) in updateDispatched() argument
228 for (WriteState &Def : getDefs()) in cycleEvent()
229 Def.cycleEvent(); in cycleEvent()
237 for (WriteState &Def : getDefs()) in cycleEvent()
238 Def.cycleEvent(); in cycleEvent()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/TableGen/
H A DJSONBackend.cpp76 if (auto *Def = dyn_cast<DefInit>(&I)) { in translateInit() local
78 obj["def"] = Def->getDef()->getName(); in translateInit()
139 auto &Def = *D.second; in run() local
144 for (const RecordVal &RV : Def.getValues()) { in run()
145 if (!Def.isTemplateArg(RV.getNameInit())) { in run()
156 for (const auto &SuperPair : Def.getSuperClasses()) in run()
161 obj["!anonymous"] = Def.isAnonymous(); in run()
166 for (const auto &SuperPair : Def.getSuperClasses()) { in run()
/netbsd-src/external/apache2/llvm/dist/clang/lib/Lex/
H A DMacroInfo.cpp205 for (DefInfo Def = getDefinition(); Def; Def = Def.getPreviousDefinition()) { in findDirectiveAtLoc() local
206 if (Def.getLocation().isInvalid() || // For macros defined on the command line. in findDirectiveAtLoc()
207 SM.isBeforeInTranslationUnit(Def.getLocation(), L)) in findDirectiveAtLoc()
208 return (!Def.isUndefined() || in findDirectiveAtLoc()
209 SM.isBeforeInTranslationUnit(L, Def.getUndefLocation())) in findDirectiveAtLoc()
210 ? Def : DefInfo(); in findDirectiveAtLoc()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-pdbutil/
H A DMinimalSymbolDumper.cpp575 CVSymbol &CVR, DefRangeFramePointerRelFullScopeSym &Def) { in visitKnownRecord() argument
576 P.format(" offset = {0}", Def.Offset); in visitKnownRecord()
581 DefRangeFramePointerRelSym &Def) { in visitKnownRecord() argument
583 P.formatLine("offset = {0}, range = {1}", Def.Hdr.Offset, in visitKnownRecord()
584 formatRange(Def.Range)); in visitKnownRecord()
585 P.formatLine("gaps = {2}", Def.Hdr.Offset, in visitKnownRecord()
586 formatGaps(P.getIndentLevel() + 9, Def.Gaps)); in visitKnownRecord()
591 DefRangeRegisterRelSym &Def) { in visitKnownRecord() argument
595 formatRegisterId(Def.Hdr.Register, CompilationCPU), in visitKnownRecord()
596 int32_t(Def.Hdr.BasePointerOffset), Def.offsetInParent(), in visitKnownRecord()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp201 MachineInstr *Def = Op->getParent(); in eraseInstrWithNoUses() local
205 if (DeadInstr.find(Def) != DeadInstr.end()) in eraseInstrWithNoUses()
212 for (MachineOperand &MODef : Def->operands()) { in eraseInstrWithNoUses()
222 if (&Use == Def) in eraseInstrWithNoUses()
233 LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); in eraseInstrWithNoUses()
234 DeadInstr.insert(Def); in eraseInstrWithNoUses()
303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() local
304 if (!Def) in optimizeSDPattern()
306 if (Def->isImplicitDef()) in optimizeSDPattern()
346 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
H A DVPlanValue.h65 VPDef *Def; variable
67 VPValue(const unsigned char SC, Value *UV = nullptr, VPDef *Def = nullptr);
107 VPValue(Value *UV = nullptr, VPDef *Def = nullptr)
108 : VPValue(VPValueSC, UV, Def) {} in VPValue() argument
174 VPDef *getDef() { return Def; } in getDef()
308 V->Def = nullptr; in removeDefinedValue()
338 assert(D->Def == this && in ~VPDef()
342 D->Def = nullptr; in ~VPDef()

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