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Searched refs:DPP (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp299 {Identity, V, B.getInt32(DPP::ROW_XMASK0 | 1 << Idx), in buildReduction()
336 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx), in buildScan()
344 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa), in buildScan()
349 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc), in buildScan()
364 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
373 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
392 {Identity, V, B.getInt32(DPP::WAVE_SHR1), B.getInt32(0xf), in buildShiftRight()
404 {Identity, V, B.getInt32(DPP::ROW_SHR0 + 1), in buildShiftRight()
H A DVOPInstructions.td625 let DPP = 1;
640 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
644 let DecoderNamespace = "DPP";
690 let DPP = 1;
696 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
700 let DecoderNamespace = "DPP";
722 let DPP = 1;
728 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
H A DSIDefines.h42 DPP = 1 << 15, enumerator
250 DPP = 4 enumerator
672 namespace DPP {
H A DGCNHazardRecognizer.h76 int checkDPPHazards(MachineInstr *DPP);
H A DAMDGPU.td416 "Support DPP (Data Parallel Primitives) extension"
429 "Support DPP (Data Parallel Primitives) extension"
1121 string DPP = "DPP";
1150 let Name = AMDGPUAsmVariants.DPP;
H A DSIInstrFormats.td35 field bit DPP = 0;
162 let TSFlags{15} = DPP;
H A DSIInstrInfo.h607 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
611 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
H A DSIInstrInfo.td1577 // Return type of input modifiers operand specified input operand for DPP
1810 // Outs for DPP
2026 0, // NumSrcArgs == 3 - No DPP for VOP3
2036 // Function that checks if instruction supports DPP and SDWA
2410 // Maps ordinary instructions to their DPP counterparts
2416 let ValueCols = [["DPP"]];
H A DGCNHazardRecognizer.cpp638 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { in checkDPPHazards() argument
650 for (const MachineOperand &Use : DPP->uses()) { in checkDPPHazards()
H A DVOP1Instructions.td109 // We only want to set this on the basic, non-SDWA or DPP forms.
H A DVOP3Instructions.td920 // (they do not support SDWA or DPP).
H A DSIInstrInfo.cpp4255 using namespace AMDGPU::DPP; in verifyInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DAMDGPUInstructionSyntax.rst126 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
136 *DPP* encoding _dpp
H A DAMDGPUModifierSyntax.rst1035 DPP Modifiers
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h895 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST; in isLegal64BitDPPControl()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp374 } else if (Flags & SIInstrFlags::DPP) { in printVOPDst()
807 using namespace AMDGPU::DPP; in printDPPCtrl()
928 using namespace llvm::AMDGPU::DPP; in printFI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3058 (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) || in checkTargetMatchPredicate()
3084 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, AMDGPUAsmVariants::DPP in getAllVariants()
3109 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP}; in getMatchedVariants()
7649 using namespace AMDGPU::DPP; in isDPPCtrl()
7848 using namespace AMDGPU::DPP; in parseDPPCtrlSel()
7896 using namespace AMDGPU::DPP; in parseDPPCtrl()
8003 using namespace llvm::AMDGPU::DPP; in cvtDPP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp405 using namespace llvm::AMDGPU::DPP; in isValidDPP8()
/netbsd-src/etc/
H A Dservices2604 groove-dpp 1211/tcp # Groove DPP [Ken_Moore] …
2605 groove-dpp 1211/udp # Groove DPP [Ken_Moore] …
/netbsd-src/external/historical/nawk/dist/testdir/
H A Dfunstack.in10664 @Article{Gelenbe:1973:DPP,