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Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_reg.h327 #define DPLL_VGA_MODE_DIS (1 << 28) macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_display.c1491 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1525 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1565 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1577 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_disable_pll()
1594 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_disable_pll()
8186 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_compute_dpll()
8203 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in chv_compute_dpll()
8485 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
8559 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
17713 DPLL_VGA_MODE_DIS | in i830_enable_pipe()
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H A Dintel_display_power.c1276 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h3382 #define DPLL_VGA_MODE_DIS (1 << 28) macro