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Searched refs:DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h38196 #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48281 #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT … macro