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Searched refs:DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h36563 #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT … macro
H A Ddcn_1_0_sh_mask.h31330 #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h40515 #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h38218 #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT … macro