| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 266 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
279 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
290 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
303 (ins SReg_256:$srsrc, DMask:$dmask,
392 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
406 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
418 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
431 (ins SReg_256:$srsrc, DMask:$dmask,
510 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
523 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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| H A D | SILoadStoreOptimizer.cpp | 105 unsigned DMask; member
517 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
697 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
698 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1224 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1534 assert("No overlaps" && (countPopulation(CI.DMask | Paired.DMask) == Width)); in getNewOpcode()
1547 assert((countPopulation(CI.DMask | Paired.DMask) == CI.Width + Paired.Width) && in getSubRegIdxs()
1549 ReverseOrder = CI.DMask > Paired.DMask; in getSubRegIdxs()
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 980 ConstantInt *DMask = cast<ConstantInt>(II.getArgOperand(DMaskIdx)); in simplifyAMDGCNMemoryIntrinsicDemanded() local
981 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
998 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | AMDGPULegalizerInfo.cpp | 4131 unsigned DMask = 0; in legalizeImageIntrinsic() local
4143 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
4146 } else if (DMask != 0) { in legalizeImageIntrinsic()
4147 DMaskLanes = countPopulation(DMask); in legalizeImageIntrinsic()
4167 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
4168 DMask = 0x1; in legalizeImageIntrinsic()
4170 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 1508 unsigned DMask = 0; in selectImageIntrinsic() local
1524 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
1527 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
1531 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
1532 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in selectImageIntrinsic()
1676 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
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| H A D | SIISelLowering.cpp | 1051 unsigned DMask in getTgtMemIntrinsic() local
1053 DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); in getTgtMemIntrinsic()
1068 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1069 unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); in getTgtMemIntrinsic()
5986 unsigned DMask; in lowerImage() local
6001 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
6004 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
6010 DMask = DMaskConst->getZExtValue(); in lowerImage()
6011 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in lowerImage()
6189 DMask = 0x1; in lowerImage()
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| H A D | SIInstrInfo.td | 1133 def DMask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
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| H A D | SIInstrInfo.cpp | 3931 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
3932 if (DMask) { in verifyInstruction()
3933 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3395 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
3396 if (DMask == 0) in validateMIMGDataSize()
3397 DMask = 1; in validateMIMGDataSize()
3400 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); in validateMIMGDataSize()
3465 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
3471 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
3483 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
3490 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 744 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
745 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); in convertMIMGInst()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 750 // Marker class for intrinsics with a DMask that determines the returned
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 37978 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
37980 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
37981 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
37985 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
38000 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
38011 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
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