Searched refs:DMACSR_COMPLETE (Results 1 – 6 of 6) sorted by relevance
242 (DMACSR_BUSEXC | DMACSR_COMPLETE in en_put()248 if (state & (DMACSR_COMPLETE|DMACSR_BUSEXC)) { in en_put()261 if ((state & DMACSR_COMPLETE) == 0 || in en_put()339 (DMACSR_BUSEXC | DMACSR_COMPLETE in en_get()347 if (state & DMACSR_COMPLETE) { in en_get()355 if ((state & DMACSR_COMPLETE) == 0 || in en_get()
401 state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE in dma_done()411 while (!(state & DMACSR_COMPLETE) && (state & DMACSR_ENABLE) && flushcount < 16) in dma_done()422 state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE in dma_done()
78 #define DMACSR_COMPLETE 0x08000000 /* current dma has completed */ macro
92 #define DMACSR_COMPLETE 0x08000000 /* current dma has completed */ macro
303 state &= (DMACSR_COMPLETE | DMACSR_SUPDATE | DMACSR_ENABLE); in nextdma_init()305 state &= (DMACSR_BUSEXC | DMACSR_COMPLETE | in nextdma_init()591 if (/* (state & DMACSR_READ) || */ (state & DMACSR_COMPLETE) == 0) { in nextdma_enet_intr()
1472 if (state & DMACSR_COMPLETE) in esp_dma_int()1497 ((state & DMACSR_COMPLETE) != 0) && in esp_dma_int()1510 if ((state & DMACSR_COMPLETE) != 0 && in esp_dma_int()