Searched refs:DIVUW (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoM.td | 20 def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDT_RISCVIntBinOpW>;
51 def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
79 def : PatGprGpr<riscv_divuw, DIVUW>;
83 // in fewer instructions than emitting DIVUW/REMUW then zero-extending the
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| H A D | RISCVISelLowering.h | 54 DIVUW, enumerator
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| H A D | RISCVISelLowering.cpp | 4576 return RISCVISD::DIVUW; in getRISCVWOpcode()
6093 case RISCVISD::DIVUW: { in computeKnownBitsForTargetNode()
6150 case RISCVISD::DIVUW: in ComputeNumSignBitsForTargetNode()
7901 NODE_NAME_CASE(DIVUW) in getTargetNodeName()
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| /netbsd-src/sys/arch/m68k/m68k/ |
| H A D | db_disasm.c | 1198 } else if (IS_INST(DIVSW,opc) || IS_INST(DIVUW,opc)) { in opcode_1000()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.td | 1206 let cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;
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