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Searched refs:DIDT_TD_CTRL0__PHASE_OFFSET_MASK (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu7_powertune.c192 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
334 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
476 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
620 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
804 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD…
H A Damdgpu_vega10_powertune.c229 …{ ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFF…
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h18361 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_1_sh_mask.h21205 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_0_sh_mask.h20599 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h29208 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_2_1_sh_mask.h30694 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_1_sh_mask.h30420 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_10_1_0_sh_mask.h43453 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK … macro