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Searched refs:DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_sh_mask.h30435 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK … macro
H A Dgc_10_1_0_sh_mask.h43101 #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK … macro