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Searched refs:DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/df/
H A Ddf_3_6_sh_mask.h49 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_df_v3_6.c355 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; in df_v3_6_get_fb_channel_number()