| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 245 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
257 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
268 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
381 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
398 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
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| H A D | MachineOutliner.cpp | 826 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
832 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
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| H A D | MachineInstr.cpp | 108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); in addImplicitDefUseOperands()
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); in addImplicitDefUseOperands()
1935 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2002 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2039 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 647 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
695 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
806 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
855 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
861 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
874 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
880 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
908 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
910 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
927 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
[all …]
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| H A D | FunctionLoweringInfo.cpp | 374 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
399 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 216 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
223 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
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| H A D | ARMBaseInstrInfo.h | 543 MachineOperand::CreateReg(PredReg, false)}};
549 return MachineOperand::CreateReg(CCReg, false);
556 return MachineOperand::CreateReg(ARM::CPSR,
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| H A D | ARMSLSHardening.cpp | 332 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
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| H A D | Thumb2InstrInfo.cpp | 569 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
601 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixVGPRCopies.cpp | 59 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
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| H A D | PPCPreEmitPeephole.cpp | 333 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
335 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 460 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 199 Register CreateReg(MVT VT, bool isDivergent = false);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 198 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon2a5e3db90111::MSP430Operand
459 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 206 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon484a835d0111::AVROperand
396 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 596 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonf0f8b3610211::VEOperand
1435 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1)); in parseOperand()
1436 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2)); in parseOperand()
1494 Op = VEOperand::CreateReg(RegNo, S, E); in parseVEAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SLSHardening.cpp | 369 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertBLRToBL()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 86 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
92 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1881 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() function in __anon65f0dadd0111::AArch64Operand
1908 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
3607 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
3626 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
3643 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
3658 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4826 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
4989 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
5005 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
5022 Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEInfo.cpp | 353 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 438 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anon6f8db8bd0211::SparcOperand
954 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
1014 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 2506 Operands.push_back(X86Operand::CreateReg(RegNo, Start, End)); in ParseIntelOperand()
2668 Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc)); in ParseATTOperand()
2792 X86Operand::CreateReg(RegNo, StartLoc, StartLoc)); in HandleAVX512Operand()
3436 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc); in ParseInstruction()
3448 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in ParseInstruction()
3457 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in ParseInstruction()
3471 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), in ParseInstruction()
3482 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); in ParseInstruction()
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