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Searched refs:CSR_WRITE_4 (Results 1 – 25 of 46) sorted by relevance

12

/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dskg.c50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
229 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */ in skg_init()
252 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON); in skg_init()
254 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON); in skg_init()
274 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET); in skg_init()
275 CSR_WRITE_4(l, SK_RXRB1_START, 0); in skg_init()
276 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0); in skg_init()
277 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0); in skg_init()
278 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff); in skg_init()
279 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_ON); in skg_init()
[all …]
H A Dkse.c48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
177 CSR_WRITE_4(l, TDLB, VTOPHYS(txd)); in kse_init()
178 CSR_WRITE_4(l, RDLB, VTOPHYS(rxd)); in kse_init()
179 CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */ in kse_init()
180 CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */ in kse_init()
181 CSR_WRITE_4(l, MDRSC, 01); /* start receiving */ in kse_init()
199 CSR_WRITE_4(l, MDTSC, 01); /* start transmission */ in kse_send()
241 CSR_WRITE_4(l, MDRSC, 01); /* restart receiving */ in kse_recv()
254 CSR_WRITE_4(l, MDRSC, 01); /* necessary? */ in kse_recv()
H A Drge.c51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
173 CSR_WRITE_4(l, RGE_IDR0, reg); in rge_init()
175 CSR_WRITE_4(l, RGE_IDR4, reg); in rge_init()
221 CSR_WRITE_4(l, RGE_TCR, l->tcr); in rge_init()
222 CSR_WRITE_4(l, RGE_RCR, l->rcr); in rge_init()
223 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd)); in rge_init()
224 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd)); in rge_init()
225 CSR_WRITE_4(l, RGE_TNPDS + 4, 0); in rge_init()
226 CSR_WRITE_4(l, RGE_RDSAR + 4, 0); in rge_init()
319 CSR_WRITE_4(l, RGE_PHYAR, v); in mii_read()
[all …]
H A Dpcn.c48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
160 CSR_WRITE_4(l, PCN_RDP, 0); in pcn_init()
313 CSR_WRITE_4(l, PCN_RAP, r); in pcn_csr_read()
320 CSR_WRITE_4(l, PCN_RAP, r); in pcn_csr_write()
321 CSR_WRITE_4(l, PCN_RDP, v); in pcn_csr_write()
327 CSR_WRITE_4(l, PCN_RAP, r); in pcn_bcr_read()
334 CSR_WRITE_4(l, PCN_RAP, r); in pcn_bcr_write()
335 CSR_WRITE_4(l, PCN_BDP, v); in pcn_bcr_write()
H A Dfxp.c93 #define CSR_WRITE_4(l, r, v) out32rb((l)->iobase+(r), (v)) macro
202 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); in fxp_init()
220 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); in fxp_init()
276 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cbp)); in fxp_init()
299 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cb_ias)); in fxp_init()
320 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(rfa)); in fxp_init()
351 CSR_WRITE_4(l, FXP_CSR_SCB_GENERAL, VTOPHYS(txd)); in fxp_send()
517 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, in fxp_mdi_read()
H A Dstg.c45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
234 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0); in stg_init()
235 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd)); in stg_init()
236 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0); in stg_init()
237 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd)); in stg_init()
239 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */ in stg_init()
272 CSR_WRITE_4(l, STGE_MACCtrl, macctl); in stg_init()
302 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow); in stg_send()
364 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset | in stg_reset()
/netbsd-src/sys/dev/pci/
H A Dif_et.c243 CSR_WRITE_4(sc, ET_PM, pmcfg); in et_attach()
368 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
372 CSR_WRITE_4(sc, ET_MII_ADDR, data); in et_miibus_readreg()
375 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); in et_miibus_readreg()
400 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_readreg()
414 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
418 CSR_WRITE_4(sc, ET_MII_ADDR, data); in et_miibus_writereg()
421 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE)); in et_miibus_writereg()
441 CSR_WRITE_4(sc, ET_MII_CMD, 0); in et_miibus_writereg()
515 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); in et_miibus_statchg()
[all …]
H A Dif_alc.c218 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_813x()
250 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_mii_readreg_816x()
289 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_813x()
318 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_mii_writereg_816x()
373 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); in alc_miibus_statchg()
415 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_readreg()
421 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in alc_miiext_readreg()
446 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | in alc_miiext_writereg()
452 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in alc_miiext_writereg()
632 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); in alc_get_macaddr_813x()
[all …]
H A Dif_ti.c363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); in ti_mem()
413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); in ti_loadfw()
432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); in ti_loadfw()
452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); in ti_cmd()
454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); in ti_cmd()
470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); in ti_cmd_ext()
473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), in ti_cmd_ext()
477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); in ti_cmd_ext()
532 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); in ti_handle_events()
1042 CSR_WRITE_4(s in ti_init_tx_ring()
[all...]
H A Dif_ale.c151 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in ale_miibus_readreg()
191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in ale_miibus_writereg()
248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_miibus_statchg()
299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); in ale_get_macaddr()
308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
1079 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, in ale_start()
1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); in ale_mac_config()
1295 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); in ale_intr()
1323 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); in ale_intr()
1580 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); in ale_reset()
[all …]
H A Dif_bge.c607 CSR_WRITE_4(sc, off, val); in bge_writemem_direct()
616 CSR_WRITE_4(sc, off, val); in bge_writembx()
953 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); in bge_nvram_getbyte()
964 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); in bge_nvram_getbyte()
966 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); in bge_nvram_getbyte()
967 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); in bge_nvram_getbyte()
987 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); in bge_nvram_getbyte()
1041 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); in bge_eeprom_getbyte()
1247 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1248 CSR_WRITE_4(s
[all...]
H A Dif_age.c358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | in age_miibus_readreg()
390 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | in age_miibus_writereg()
446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_miibus_statchg()
449 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); in age_miibus_statchg()
505 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); in age_intr()
514 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); in age_intr()
571 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); in age_get_macaddr()
580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
615 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); in age_phy_reset()
617 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); in age_phy_reset()
[all …]
H A Dif_iwi.c153 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); in MEM_READ_1()
160 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); in MEM_READ_4()
251 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); in iwi_attach()
1200 CSR_WRITE_4(sc, IWI_CSR_RX_BASE + i * 4, data->map->dm_segs[0].ds_addr); in iwi_frame_intr()
1381 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, in iwi_cmd_intr()
1429 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw); in iwi_rx_intr()
1485 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); in iwi_intr()
1502 CSR_WRITE_4(sc, IWI_CSR_INTR, r); in iwi_softintr()
1550 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); in iwi_softintr()
1577 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur); in iwi_cmd()
[all …]
H A Dif_ipwreg.h328 #define CSR_WRITE_4(sc, reg, val) \ macro
339 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
344 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
349 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
350 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
354 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
H A Dif_ipw.c138 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); in MEM_READ_1()
145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); in MEM_READ_4()
209 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_attach()
1174 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); in ipw_rx_intr()
1260 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_intr()
1297 CSR_WRITE_4(sc, IPW_CSR_INTR, r); in ipw_softintr()
1301 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); in ipw_softintr()
1340 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); in ipw_cmd()
1504 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); in ipw_tx_start()
1593 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); in ipw_get_table1()
[all …]
H A Dif_stge.c223 #define CSR_WRITE_4(_sc, reg, val) \ macro
997 CSR_WRITE_4(sc, STGE_DMACtrl, in stge_start()
1487 CSR_WRITE_4(sc, STGE_AsicCtrl, in stge_reset()
1576 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); in stge_init()
1577 CSR_WRITE_4(sc, STGE_StatisticsMask, in stge_init()
1589 CSR_WRITE_4(sc, STGE_TFDListPtrHi, in stge_init()
1591 CSR_WRITE_4(sc, STGE_TFDListPtrLo, in stge_init()
1594 CSR_WRITE_4(sc, STGE_RFDListPtrHi, in stge_init()
1596 CSR_WRITE_4(sc, STGE_RFDListPtrLo, in stge_init()
1630 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, in stge_init()
[all …]
H A Dif_kse.c67 #define CSR_WRITE_4(sc, off, val) \ macro
764 CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0)); in kse_init()
765 CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0)); in kse_init()
813 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); in kse_init()
814 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); in kse_init()
815 CSR_WRITE_4(sc, MDRSC, 1); in kse_init()
821 CSR_WRITE_4(sc, INTST, ~0); in kse_init()
822 CSR_WRITE_4(sc, INTEN, sc->sc_inten); in kse_init()
854 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); in kse_stop()
855 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); in kse_stop()
[all …]
H A Dif_iwireg.h552 #define CSR_WRITE_4(sc, reg, val) \ macro
563 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
568 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
573 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
574 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
578 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
H A Dif_vge.c260 #define CSR_WRITE_4(sc, reg, val) \ macro
279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))
286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))
650 CSR_WRITE_4(sc, VGE_MAR0, 0); in vge_setmulti()
651 CSR_WRITE_4(sc, VGE_MAR1, 0); in vge_setmulti()
660 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); in vge_setmulti()
661 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); in vge_setmulti()
711 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); in vge_setmulti()
712 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); in vge_setmulti()
1476 CSR_WRITE_4(sc, VGE_ISR, status); in vge_intr()
[all …]
H A Dif_vr.c286 #define CSR_WRITE_4(sc, reg, val) \ macro
345 CSR_WRITE_4(sc, reg, \
349 CSR_WRITE_4(sc, reg, \
478 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); in vr_setmulti()
479 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); in vr_setmulti()
484 CSR_WRITE_4(sc, VR_MAR0, 0); in vr_setmulti()
485 CSR_WRITE_4(sc, VR_MAR1, 0); in vr_setmulti()
515 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); in vr_setmulti()
516 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); in vr_setmulti()
823 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); in vr_rxeoc()
[all …]
/netbsd-src/sys/arch/arm/xscale/
H A Dixp425_pci_space.c53 #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \ macro
270 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); in _pci_io_bs_r_1()
271 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); in _pci_io_bs_r_1()
274 CSR_WRITE_4(PCI_ISR, ISR_PFE); in _pci_io_bs_r_1()
290 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); in _pci_io_bs_r_2()
291 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); in _pci_io_bs_r_2()
294 CSR_WRITE_4(PCI_ISR, ISR_PFE); in _pci_io_bs_r_2()
307 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); in _pci_io_bs_r_4()
308 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); in _pci_io_bs_r_4()
311 CSR_WRITE_4(PCI_ISR, ISR_PFE); in _pci_io_bs_r_4()
[all …]
H A Dpxa2x0_mci.c151 #define CSR_WRITE_4(sc, reg, val) \ macro
154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
173 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); in pxamci_enable_intr()
184 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); in pxamci_disable_intr()
358 CSR_WRITE_4(sc, MMC_SPI, 0); in pxamci_host_reset()
359 CSR_WRITE_4(sc, MMC_RESTO, 0x7f); in pxamci_host_reset()
360 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask); in pxamci_host_reset()
511 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt); in pxamci_bus_clock()
512 CSR_WRITE_4(sc, MMC_STRPCL, STRPCL_START); in pxamci_bus_clock()
[all …]
H A Dpxa2x0_i2c.c408 #define CSR_WRITE_4(sc,r,v) bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v) macro
420 CSR_WRITE_4(sc, I2C_ICR, ICR_UR); in pxa2x0_i2c_reset()
421 CSR_WRITE_4(sc, I2C_ISAR, 0); in pxa2x0_i2c_reset()
422 CSR_WRITE_4(sc, I2C_ISR, ISR_ALL); in pxa2x0_i2c_reset()
425 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr); in pxa2x0_i2c_reset()
449 CSR_WRITE_4(sc, I2C_ISR, isr); in pxa2x0_i2c_wait()
458 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START); in pxa2x0_i2c_send_start()
467 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_STOP); in pxa2x0_i2c_send_stop()
483 CSR_WRITE_4(sc, I2C_IDBR, (addr << 1) | rd_req); in pxa2x0_i2c_initiate_xfer()
484 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START | ICR_TB); in pxa2x0_i2c_initiate_xfer()
[all …]
/netbsd-src/sys/dev/ic/
H A Drtl81x9.c540 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); in rtk_setmulti()
541 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); in rtk_setmulti()
542 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); in rtk_setmulti()
547 CSR_WRITE_4(sc, RTK_MAR0, 0); in rtk_setmulti()
548 CSR_WRITE_4(sc, RTK_MAR4, 0); in rtk_setmulti()
578 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); in rtk_setmulti()
587 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); in rtk_setmulti()
588 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); in rtk_setmulti()
590 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); in rtk_setmulti()
591 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); in rtk_setmulti()
[all …]
H A Drtl8169.c247 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); in re_gmii_readreg()
273 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | in re_gmii_writereg()
1495 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); in re_txeof()
1841 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); in re_start()
1921 CSR_WRITE_4(sc, RTK_IDR0, reg); in re_init()
1923 CSR_WRITE_4(sc, RTK_IDR4, reg); in re_init()
1936 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, in re_init()
1938 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, in re_init()
1941 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, in re_init()
1943 CSR_WRITE_4(s in re_init()
[all...]

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