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Searched refs:CSR_READ_2 (Results 1 – 25 of 40) sorted by relevance

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/netbsd-src/sys/dev/pci/
H A Dif_vte.c347 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) in vte_miibus_readreg()
356 *val = CSR_READ_2(sc, VTE_MMRD); in vte_miibus_readreg()
371 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) in vte_miibus_writereg()
444 mid = CSR_READ_2(sc, VTE_MID0L); in vte_get_macaddr()
447 mid = CSR_READ_2(sc, VTE_MID0M); in vte_get_macaddr()
450 mid = CSR_READ_2(sc, VTE_MID0H); in vte_get_macaddr()
873 mcr = CSR_READ_2(sc, VTE_MCR0); in vte_mac_config()
898 CSR_READ_2(sc, VTE_CNT_RX_DONE); in vte_stats_clear()
899 CSR_READ_2(sc, VTE_CNT_MECNT0); in vte_stats_clear()
900 CSR_READ_2(s in vte_stats_clear()
[all...]
H A Dif_kse.c69 #define CSR_READ_2(sc, off) \ macro
436 i = CSR_READ_2(sc, MARL); in kse_attach()
439 i = CSR_READ_2(sc, MARM); in kse_attach()
442 i = CSR_READ_2(sc, MARH); in kse_attach()
801 i = CSR_READ_2(sc, SGCR3); in kse_init()
1331 uint16_t p1sr = CSR_READ_2(sc, P1SR); in lnkchg()
1382 printf("p1sr: %04x, p2sr: %04x\n", CSR_READ_2(sc, P1SR), CSR_READ_2(sc, P2SR)); in nopifmedia_sts()
1425 *val = CSR_READ_2(sc, phy1csr[reg]); in kse_mii_readreg()
1448 uint16_t p1sr = CSR_READ_2(sc, P1SR); in kse_mii_statchg()
1512 val = CSR_READ_2(sc, IADR5) << 16; in stat_tick()
[all …]
H A Dif_stge.c232 #define CSR_READ_2(_sc, reg) \ macro
585 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff; in stge_attach()
586 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8; in stge_attach()
587 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff; in stge_attach()
588 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8; in stge_attach()
589 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff; in stge_attach()
590 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8; in stge_attach()
1102 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) in stge_intr()
1106 isr = CSR_READ_2(sc, STGE_IntStatusAck); in stge_intr()
1450 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors)); in stge_stats_update()
[all …]
H A Dif_vr.c295 #define CSR_READ_2(sc, reg) \ macro
338 CSR_READ_2(sc, reg) | (x))
342 CSR_READ_2(sc, reg) & ~(x))
425 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON)) in vr_mii_statchg()
440 if (!(CSR_READ_2(sc, VR_COMMAND) & in vr_mii_statchg()
529 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) in vr_reset()
813 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) in vr_rxeoc()
859 if ((CSR_READ_2(sc, VR_COMMAND) & in vr_txeof()
929 status = CSR_READ_2(sc, VR_ISR); in vr_intr()
H A Dif_vtevar.h157 #define CSR_READ_2(_sc, reg) \ macro
H A Dif_vge.c269 #define CSR_READ_2(sc, reg) \ macro
277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
397 word = CSR_READ_2(sc, VGE_EERDDAT); in vge_read_eeprom()
496 *val = CSR_READ_2(sc, VGE_MIIDATA); in vge_miibus_readreg()
H A Dif_ipwreg.h316 #define CSR_READ_2(sc, reg) \ macro
/netbsd-src/sys/arch/evbarm/stand/boot2440/
H A Ddm9000.c141 CSR_READ_2(struct local *l, int reg) in CSR_READ_2() function
348 (void) CSR_READ_2(l, MRCMDX); /* dummy read */ in dm9k_recv()
349 mark = CSR_READ_2(l, MRCMDX); /* mark in [7:0] */ in dm9k_recv()
357 stat = CSR_READ_2(l, MRCMD); /* stat in [15:8] */ in dm9k_recv()
358 len = CSR_READ_2(l, MRCMD); in dm9k_recv()
363 (void) CSR_READ_2(l, MRCMD); in dm9k_recv()
373 val = CSR_READ_2(l, MRCMD); in dm9k_recv()
380 (void) CSR_READ_2(l, MRCMD); in dm9k_recv()
/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dkse.c49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
138 i = CSR_READ_2(l, MARL); in kse_init()
141 i = CSR_READ_2(l, MARM); in kse_init()
144 i = CSR_READ_2(l, MARH); in kse_init()
157 val = CSR_READ_2(l, P1SR); in kse_init()
267 val = CSR_READ_2(l, P1SR); in mii_dealan()
H A Dstg.c44 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
197 addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData)); in stg_init()
245 CSR_READ_2(l, STGE_DebugCtrl) | 0x0200); in stg_init()
247 CSR_READ_2(l, STGE_DebugCtrl) | 0x0010); in stg_init()
249 CSR_READ_2(l, STGE_DebugCtrl) | 0x0020); in stg_init()
552 if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0) in eeprom_wait()
H A Dskg.c49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
321 reg = CSR_READ_2(l, YUKON_GPCR); in skg_init()
408 v = CSR_READ_2(l, YUKON_SMICR); in mii_read()
414 return CSR_READ_2(l, YUKON_SMIDR); in mii_read()
428 v = CSR_READ_2(l, YUKON_SMICR); in mii_write()
H A Dfxp.c92 #define CSR_READ_2(l, r) in16rb((l)->iobase+(r)) macro
449 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & in autosize_eeprom()
487 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & in read_eeprom()
H A Dnvt.c50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
355 v = CSR_READ_2(l, VR_MIIDATA); in mii_read()
H A Dpcn.c49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
156 (void)CSR_READ_2(l, PCN_16RESET); in pcn_init()
H A Dvge.c50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) macro
437 v = CSR_READ_2(l, VR_MIIDATA); in mii_read()
/netbsd-src/sys/dev/ic/
H A Dan.c494 if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) { in an_softintr()
496 CSR_READ_2(sc, AN_SW0))); in an_softintr()
500 status = CSR_READ_2(sc, AN_EVENT_STAT); in an_softintr()
1384 fid = CSR_READ_2(sc, AN_RX_FID); in an_rx_intr()
1544 fid = CSR_READ_2(sc, AN_TX_CMP_FID); in an_tx_intr()
1583 status = CSR_READ_2(sc, AN_LINKSTAT); in an_linkstat_intr()
1606 if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) { in an_cmd()
1609 CSR_READ_2(sc, AN_COMMAND)); in an_cmd()
1624 if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD) in an_cmd()
1629 status = CSR_READ_2(sc, AN_STATUS); in an_cmd()
[all …]
H A Dbwivar.h82 #define CSR_READ_2(sc, reg) \ macro
97 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
102 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
107 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Drtl81x9.c324 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; in rtk_mii_readreg()
347 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) in rtk_mii_readreg()
450 *val = CSR_READ_2(sc, rtk8139_reg); in rtk_phy_readreg()
923 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; in rtk_rxeof()
926 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; in rtk_rxeof()
1183 status = CSR_READ_2(sc, RTK_ISR); in rtk_intr()
H A Dwivar.h243 #define CSR_READ_2(sc, reg) \ macro
265 #define CSR_READ_2(sc, reg) \ macro
H A Dwi.c655 status = CSR_READ_2(sc, WI_EVENT_STAT); in wi_intr()
691 status = CSR_READ_2(sc, WI_EVENT_STAT); in wi_softintr()
1661 fid = CSR_READ_2(sc, WI_RX_FID); in wi_rx_intr()
1788 fid = CSR_READ_2(sc, WI_TX_CMP_FID); in wi_tx_ex_intr()
1864 fid = CSR_READ_2(sc, WI_ALLOC_FID); in wi_txalloc_intr()
1969 fid = CSR_READ_2(sc, WI_TX_CMP_FID); in wi_tx_intr()
2024 fid = CSR_READ_2(sc, WI_INFO_FID); in wi_info_intr()
2783 if ((CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY) == 0) in wi_cmd_start()
2873 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD) in wi_cmd_wait()
2895 status = CSR_READ_2(sc, WI_STATUS); in wi_cmd_wait()
[all …]
H A Danvar.h53 #define CSR_READ_2(sc, reg) \ macro
H A Dbwi.c1218 return (CSR_READ_2(sc, data_reg)); in bwi_mac_lateattach()
1232 ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN); in bwi_mac_lateattach()
1237 ret |= CSR_READ_2(sc, BWI_MOBJ_DATA); in bwi_mac_lateattach()
1784 if (CSR_READ_2(sc, 0x50e) & 0x80) in bwi_mac_init_tpctl_11bg()
1789 if (CSR_READ_2(sc, 0x50e) & 0x400) in bwi_mac_init_tpctl_11bg()
1794 if ((CSR_READ_2(sc, 0x690) & 0x100) == 0) in bwi_mac_init_tpctl_11bg()
3012 CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */ in bwi_phy_attach()
3057 return (CSR_READ_2(sc, BWI_PHY_DATA)); in bwi_phy_set_bbp_atten()
3070 val = CSR_READ_2(sc, BWI_PHYINFO); in bwi_phy_set_bbp_atten()
3987 return (CSR_READ_2(s in bwi_rf_attach()
[all...]
H A Drtl81x9var.h287 #define CSR_READ_2(sc, reg) \
286 #define CSR_READ_2( global() macro
/netbsd-src/sys/dev/pcmcia/
H A Dif_wi_pcmcia.c363 CSR_READ_2(sc, WI_COR) == WI_COR_IOMODE) in wi_pcmcia_attach()
446 if (CSR_READ_2(sc, WI_CNTL) == WI_CNTL_AUX_ENA_STAT) in wi_pcmcia_load_firm()
461 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD) in wi_pcmcia_load_firm()
547 hcr = CSR_READ_2(sc, WI_HCR); in wi_pcmcia_set_hcr()
/netbsd-src/sys/arch/evbarm/ixm1200/
H A Dnappi_nppb.c60 #define CSR_READ_2(sc, reg) \ macro

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