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Searched refs:CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2905 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h2462 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h3528 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h3006 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19214 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20452 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT … macro
H A Dgc_9_1_sh_mask.h20525 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h26976 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT … macro