Home
last modified time | relevance | path

Searched refs:CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h4491 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
H A Dgfx_8_0_sh_mask.h3969 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12916 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_2_1_sh_mask.h14085 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_1_sh_mask.h14220 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_10_1_0_sh_mask.h20200 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro