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Searched refs:CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2094 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L macro
H A Dgfx_7_2_sh_mask.h3203 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
H A Dgfx_8_1_sh_mask.h4339 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
H A Dgfx_8_0_sh_mask.h3817 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1320 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_9_2_1_sh_mask.h1186 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_9_1_sh_mask.h1219 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_10_1_0_sh_mask.h6802 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro