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Searched refs:CPU_CONTROL_IC_ENABLE (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/sys/arch/arm/arm/
H A Dcpufunc.c2641 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2642 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2643 { "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2644 { "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
2658 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE in arm9_setup()
2662 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE in arm9_setup()
2694 { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2695 { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2696 { "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
2697 { "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
[all …]
H A Darmv6_start.S673 CPU_CONTROL_IC_ENABLE | \
994 ldr r2, =(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
/netbsd-src/sys/arch/evbarm/stand/board/
H A Ds3c2410_vector.S73 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
87 orr r10, r10, #CPU_CONTROL_IC_ENABLE
H A Ds3c2800_vector.S105 ldr r0, =(CPU_CONTROL_MMU_ENABLE|CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
119 orr r10, r10, #CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/evbarm/armadaxp/
H A Darmadaxp_start.S74 CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_IC_ENABLE |\
119 #define CPU_CONTROL_SET (CPU_CONTROL_XP_ENABLE | CPU_CONTROL_IC_ENABLE \
/netbsd-src/sys/arch/evbarm/gemini/
H A Dgemini_start.S322 CPU_CONTROL_IC_ENABLE | \
338 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
/netbsd-src/sys/arch/hpcarm/hpcarm/
H A Dkloader_pxa2x0.S57 bic r2, r2, #CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/zaurus/zaurus/
H A Dkloader_zaurus.S70 bic r2, r2, #CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/evbarm/ixm1200/
H A Dixm1200_start.S70 orr r0, r0, #CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/evbarm/imx23_olinuxino/
H A Dimx23_olinuxino_start.S132 ldr r1, =(CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE \
/netbsd-src/sys/arch/arm/arm32/
H A Dlocore.S186 bic r0, r0, #(CPU_CONTROL_IC_ENABLE)
H A Dcpu.c743 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0) in identify_arm_cpu()
/netbsd-src/sys/arch/evbarm/marvell/
H A Dmarvell_start.S245 biceq r0, r0, #(CPU_CONTROL_IC_ENABLE)
/netbsd-src/sys/arch/epoc32/epoc32/
H A Depoc32_start.S241 CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/evbarm/armadillo/
H A Darmadillo9_start.S63 bic r2, r2, #CPU_CONTROL_IC_ENABLE
/netbsd-src/sys/arch/arm/include/
H A Darmreg.h199 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ macro