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Searched refs:CPSR (Results 1 – 25 of 80) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h106 MIB.addReg(ARM::CPSR, RegState::Define);
114 MIB.addReg(ARM::CPSR);
142 MIB.addReg(ARM::CPSR);
170 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp256 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
304 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
384 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
657 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
818 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
882 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
910 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
962 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
987 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
1002 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
[all …]
H A DARMInstrThumb.td415 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1001 /// instruction modifies the CPSR register.
1004 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1005 let hasPostISelHook = 1, Defs = [CPSR] in {
1006 let isCommutable = 1, Uses = [CPSR] in
1009 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
1010 CPSR))]>,
1016 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
[all …]
H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMBaseInstrInfo.cpp596 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
638 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
639 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
659 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
738 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
844 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
864 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
982 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
985 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2254 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
[all …]
H A DARMFastISel.cpp234 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
246 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
253 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
254 *CPSR = true; in DefinesOptionalPredicate()
291 bool CPSR = false; in AddOptionalDefs() local
292 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
293 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1251 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1274 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1312 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
[all …]
H A DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1656 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1657 let hasPostISelHook = 1, Defs = [CPSR] in {
1663 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1668 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1675 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1682 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1690 let hasPostISelHook = 1, Defs = [CPSR] in {
1696 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1702 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
[all …]
H A DARMInstrThumb2.td726 /// changed to modify CPSR.
865 /// instruction modifies the CPSR register.
868 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
869 let hasPostISelHook = 1, Defs = [CPSR] in {
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
900 let hasPostISelHook = 1, Defs = [CPSR] in {
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
[all …]
H A DThumb2ITBlockPass.cpp173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARM.td331 /// Some instructions update CPSR partially, which can add false dependency for
333 /// mapped to a separate physical register. Avoid partial CPSR update for these
337 "Avoid CPSR partial update for OOO execution">;
339 /// Disable +1 predication cost for instructions updating CPSR.
344 "Disable +1 predication cost for instructions updating CPSR">;
H A DARMInstructionSelector.cpp602 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
796 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1154 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMAsmPrinter.cpp1725 .addReg(ARM::CPSR) in emitInstruction()
1781 .addReg(ARM::CPSR) in emitInstruction()
1912 .addReg(ARM::CPSR) in emitInstruction()
1931 .addReg(ARM::CPSR) in emitInstruction()
1946 .addReg(ARM::CPSR) in emitInstruction()
H A DARMExpandPseudoInsts.cpp1031 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1155 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1644 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1667 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1759 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1765 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1787 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2102 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2304 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2499 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
H A DARMLowOverheadLoops.cpp1318 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1348 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1359 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
H A DMVETPAndVPTOptimisationsPass.cpp195 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
204 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
H A DARMISelLowering.cpp4597 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, in getARMCmp()
4754 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
4874 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
5273 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5308 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5415 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
5464 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
5518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5527 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5544 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
[all …]
H A DThumb1FrameLowering.cpp419 .addDef(ARM::CPSR) in emitPrologue()
425 .addDef(ARM::CPSR) in emitPrologue()
/netbsd-src/sys/arch/dreamcast/dev/microcode/
H A Daica_arm_locore.S45 mrs r0,CPSR /* disable interrupt */
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dfa726te.md46 ;; <-- AU --> shifter + LU CPSR (Pipe 0)
51 ;; <-- AU --> shifter + LU CPSR (Pipe 1)
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dfa726te.md46 ;; <-- AU --> shifter + LU CPSR (Pipe 0)
51 ;; <-- AU --> shifter + LU CPSR (Pipe 1)
/netbsd-src/external/gpl3/gdb.old/dist/sim/arm/
H A Darmemu.h166 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) macro
168 #define CPSR (ECC | EINT | EMODE) macro
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp191 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
239 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
/netbsd-src/external/gpl3/gdb/dist/gdb/stubs/
H A Dsparc-stub.c119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR }; enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
/netbsd-src/sys/external/bsd/gnu-efi/dist/inc/
H A Defidebug.h505 UINT32 CPSR; member

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