Home
last modified time | relevance | path

Searched refs:CNTX_BUSY_INT_ENABLE (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dnid.h497 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dsid.h1281 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dcikd.h1334 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dradeon_si.c5160 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5162 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5961 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_disable_interrupt_state()
6079 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_irq_set()
H A Dradeon_evergreen.c4470 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4476 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4499 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set()
H A Devergreend.h1249 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dradeon_cik.c5791 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_enable_gui_idle_interrupt()
5793 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_enable_gui_idle_interrupt()
6888 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_disable_interrupt_state()
7066 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_irq_set()
H A Dr600d.h717 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dradeon_r600.c3658 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3799 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h1310 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Damdgpu_gfx_v10_0.c1776 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()
H A Damdgpu_gfx_v8_0.c3884 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
H A Damdgpu_gfx_v9_0.c2565 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()