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Searched refs:BuildMI (Results 1 – 25 of 292) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp796 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
800 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
810 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
817 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
824 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
829 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
834 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
844 BuildMI(MBB, StackUpdateLoc, dl, StoreInst) in emitPrologue()
862 BuildMI(MBB, StackUpdateLoc, dl, HashST) in emitPrologue()
872 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsBranchExpansion.cpp340 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
396 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
468 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
489 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
494 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
496 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
511 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
514 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
526 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
[all …]
H A DMipsSEFrameLowering.cpp178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
[all …]
H A DMipsInstructionSelector.cpp261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
275 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
301 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
325 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
332 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
342 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
361 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)) in select()
374 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
382 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
239 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
242 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
247 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg) in doAtomicBinOpExpansion()
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
267 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
270 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp227 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
244 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg) in emitSPUpdate()
247 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
261 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
270 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax) in emitSPUpdate()
273 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
279 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
282 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
300 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
346 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
[all …]
H A DX86ExpandPseudo.cpp106 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
127 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC); in INITIALIZE_PASS()
142 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
184 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64)) in INITIALIZE_PASS()
211 OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr(); in expandCALL_RVMARKER()
231 auto *Marker = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::MOV64rr)) in expandCALL_RVMARKER()
250 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(X86::CALL64pcrel32)) in expandCALL_RVMARKER()
330 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
347 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) in emitEpilogueInsns()
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) in emitEpilogueInsns()
[all …]
H A DVEInstrInfo.cpp238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
270 BuildMI(&MBB, DL, get(opc[0])) in insertBranch()
276 BuildMI(&MBB, DL, get(opc[1])) in insertBranch()
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h328 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, in BuildMI() function
335 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, in BuildMI() function
344 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
360 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
370 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, in BuildMI() function
376 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); in BuildMI()
377 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
380 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, in BuildMI() function
383 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI()
389 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
78 BuildMI(*BB, MI, dl, get(LdOpc)) in expandMEMCPY()
81 BuildMI(*BB, MI, dl, get(StOpc)) in expandMEMCPY()
92 BuildMI(*BB, MI, dl, get(BPF::LDW)) in expandMEMCPY()
94 BuildMI(*BB, MI, dl, get(BPF::STW)) in expandMEMCPY()
99 BuildMI(*BB, MI, dl, get(BPF::LDH)) in expandMEMCPY()
101 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
106 BuildMI(*BB, MI, dl, get(BPF::LDB)) in expandMEMCPY()
108 BuildMI(*BB, MI, dl, get(BPF::STB)) in expandMEMCPY()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
104 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
121 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
129 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
146 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0); in restoreStatusRegister()
147 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)) in restoreStatusRegister()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp147 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
157 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
168 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
215 BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg) in expandCMP_SWAP()
217 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
223 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc)) in expandCMP_SWAP()
233 BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg) in expandCMP_SWAP()
236 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW)) in expandCMP_SWAP()
296 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX)) in expandCMP_SWAP_128()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in insertBranch()
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in insertBranch()
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in insertBranch()
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in insertBranch()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
[all …]
H A DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
156 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
169 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp170 BuildMI(MBB, I, DL, SMovB32, TargetHi) in buildGitPtr()
175 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
180 BuildMI(MBB, I, DL, SMovB32, TargetLo) in buildGitPtr()
247 BuildMI(MBB, I, DL, LoadDwordX2, FlatScrInit) in emitEntryFunctionFlatScratchInit()
255 BuildMI(MBB, I, DL, SAndB32, FlatScrInitHi) in emitEntryFunctionFlatScratchInit()
274 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo) in emitEntryFunctionFlatScratchInit()
277 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), FlatScrInitHi) in emitEntryFunctionFlatScratchInit()
280 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)). in emitEntryFunctionFlatScratchInit()
284 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)). in emitEntryFunctionFlatScratchInit()
292 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO) in emitEntryFunctionFlatScratchInit()
[all …]
H A DAMDGPUInstructionSelector.cpp147 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg) in selectCOPY()
158 BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg) in selectCOPY()
161 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) in selectCOPY()
243 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg) in getSubOperand64()
318 BuildMI(*BB, &I, DL, TII.get(Opc), DstReg) in selectG_ADD_SUB()
337 = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg) in selectG_ADD_SUB()
362 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) in selectG_ADD_SUB()
365 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD_SUB()
371 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_CO_U32_e64), DstLo) in selectG_ADD_SUB()
376 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi) in selectG_ADD_SUB()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp336 BuildMI(MBB, std::next(Info.I), dl, in emitDefCFAOffsets()
377 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
382 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
392 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
397 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
407 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
611 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
616 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
626 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
633 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
[all …]
H A DARMExpandPseudoInsts.cpp537 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
648 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST()
725 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp()
810 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
908 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
909 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
915 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
916 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
951 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); in ExpandMOV32BitImm()
952 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) in ExpandMOV32BitImm()
[all …]
H A DThumb1FrameLowering.cpp84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
188 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
265 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
293 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
304 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
313 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
320 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
362 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
148 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) in emitPrologue()
159 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
164 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) in emitPrologue()
173 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
186 BuildMI(MBB, MBBI, dl, in emitPrologue()
200 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
208 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp594 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc)); in createHalfInstr()
648 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first) in splitMemRef()
651 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second) in splitMemRef()
657 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
661 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
675 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR) in splitMemRef()
718 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first) in splitImmediate()
720 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitImmediate()
738 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitCombine()
741 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4); in emitEpilogue()
156 BuildMI(MBB, MBBI, DL, in emitEpilogue()
160 BuildMI(MBB, MBBI, DL, in emitEpilogue()
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
197 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
216 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); in restoreCalleeSavedRegisters()
242 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP) in eliminateCallFramePseudoInstr()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0); in InsertSPConstInst()
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