Searched refs:Bridge (Results 1 – 25 of 93) sorted by relevance
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794 product ACC 2188 0x0000 ACCM 2188 VL-PCI Bridge795 product ACC 2051_HB 0x2051 2051 PCI Single Chip Solution (host Bridge)796 product ACC 2051_ISA 0x5842 2051 PCI Single Chip Solution (ISA Bridge)816 product ACER M1435 0x1435 M1435 VL-PCI Bridge827 product ALI M1445 0x1445 M1445 VL-PCI Bridge828 product ALI M1449 0x1449 M1449 PCI-ISA Bridge829 product ALI M1451 0x1451 M1451 Host-PCI Bridge830 product ALI M1461 0x1461 M1461 Host-PCI Bridge831 product ALI M1531 0x1531 M1531 Host-PCI Bridge832 product ALI M1533 0x1533 M1533 PCI-ISA Bridge[all...]
75 * yylex (reentrant version): Bison Bridge. (line 22)76 * yylex (reentrant version) <1>: Bison Bridge. (line 27)137 * yylloc: Bison Bridge. (line 6)139 * yylval: Bison Bridge. (line 6)164 * YYLTYPE: Bison Bridge. (line 6)166 * YYSTYPE: Bison Bridge. (line 6)
12 model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
13 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
13 model = "Laird Workgroup Bridge 50N - Project Gatwick";
128 /* USB 3.0 Bridge ASM1042A */
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
106 # SigmaTel STIr4210/4220/4116 USB/IrDA Bridge - not quite UIRDA110 # SigmaTel STIr4200 USB/IrDA Bridge114 # KingSun/DonShine USB/IrDA Bridge
1 dnl X86-64 mpn_copyi optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_copyd optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_lshift optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_rshift optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_lshiftc optimised for Intel Sandy Bridge.
1 dnl AMD64 mpn_mul_2 optimised for Intel Sandy Bridge.
1 dnl AMD64 mpn_addmul_2 optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_addmul_1 and mpn_submul_1 optimised for Intel Sandy Bridge.
1 dnl X86-64 mpn_redc_1 optimised for Intel Sandy Bridge and Ivy Bridge.
3 dnl Optimised for Sandy Bridge.
1 dnl X86-64 mpn_mul_1 optimised for Intel Sandy Bridge.
114 PCI_BRIDGE_CONTROL_REGISTER Bridge; member
20 # I/O Bridge Zero attachment to ZBbus
27 # OBIO: offsets are from System Bridge Controller base
93 # PCI Root Bridge
1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//9 // This file defines the machine model for Sandy Bridge to support instruction37 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.191 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.1115 // section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and