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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.h28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
29 const BitVector &SourceBits);
44 const BitVector &ReservedReg,
51 const BitVector &sourceBits() const { return SourceBits; } in sourceBits()
54 const BitVector &aliasedBits() const { return AliasedBits; } in aliasedBits()
68 const BitVector &OriginalBits);
70 BitVector SourceBits;
71 BitVector AliasedBits;
79 const BitVector &ReservedReg);
82 const BitVector &emptyRegisters() const { return EmptyRegisters; } in emptyRegisters()
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H A DMCInstrDescView.h100 const BitVector *getUnique(BitVector &&BV) const;
103 mutable std::vector<std::unique_ptr<BitVector>> Cache;
136 bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
140 const BitVector &ForbiddenRegisters) const;
161 const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
162 const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
163 const BitVector &AllDefRegs; // The set of all aliased def registers.
164 const BitVector &AllUseRegs; // The set of all aliased use registers.
168 SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
169 const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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H A DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits()
15 const BitVector &SourceBits) { in getAliasedBits()
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker()
49 const MCRegisterInfo &RegInfo, const BitVector &SourceBits) { in FillOriginAndAliasedBits()
61 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg) in RegisterAliasingTrackerCache()
82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString()
H A DMCInstrDescView.cpp83 const BitVector *BitVectorCache::getUnique(BitVector &&BV) const { in getUnique()
87 Cache.push_back(std::make_unique<BitVector>()); in getUnique()
96 const BitVector *ImplDefRegs, in Instruction()
97 const BitVector *ImplUseRegs, in Instruction()
98 const BitVector *AllDefRegs, in Instruction()
99 const BitVector *AllUseRegs) in Instruction()
168 BitVector ImplDefRegs = RATC.emptyRegisters(); in create()
169 BitVector ImplUseRegs = RATC.emptyRegisters(); in create()
170 BitVector AllDefRegs = RATC.emptyRegisters(); in create()
171 BitVector AllUseRegs = RATC.emptyRegisters(); in create()
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H A DParallelSnippetGenerator.cpp120 const BitVector &ForbiddenRegisters) { in generateSnippetUsingStaticRenaming()
124 std::vector<BitVector> PossibleRegsForVar; in generateSnippetUsingStaticRenaming()
129 BitVector PossibleRegs = Op.getRegisterAliasing().sourceBits(); in generateSnippetUsingStaticRenaming()
149 for (BitVector &OtherPossibleRegs : PossibleRegsForVar) { in generateSnippetUsingStaticRenaming()
159 InstructionTemplate Variant, const BitVector &ForbiddenRegisters) const { in generateCodeTemplates()
189 BitVector Defs(State.getRegInfo().getNumRegs()); in generateCodeTemplates()
H A DSnippetGenerator.h65 const BitVector &ExtraForbiddenRegs) const;
79 const BitVector &ForbiddenRegisters) const = 0;
92 size_t randomBit(const BitVector &Vector);
102 const BitVector &ForbiddenRegs,
H A DSnippetGenerator.cpp43 const BitVector &ExtraForbiddenRegs) const { in generateConfigurations()
44 BitVector ForbiddenRegs = State.getRATC().reservedRegisters(); in generateConfigurations()
106 BitVector DefinedRegs = State.getRATC().emptyRegisters(); in computeRegisterInitialValues()
208 size_t randomBit(const BitVector &Vector) { in randomBit()
228 const BitVector &ForbiddenRegs) { in randomizeMCOperand()
262 const BitVector &ForbiddenRegs, in randomizeUnsetVariables()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
H A DBitVector.h74 class BitVector {
97 reference(BitVector &b, unsigned Idx) { in reference()
123 typedef const_set_bits_iterator_impl<BitVector> const_set_bits_iterator;
137 BitVector() : Size(0) {} in BitVector() function
141 explicit BitVector(unsigned s, bool t = false)
343 BitVector &set() { in set()
349 BitVector &set(unsigned Idx) { in set()
356 BitVector &set(unsigned I, unsigned E) { in set()
384 BitVector &reset() { in reset()
389 BitVector &reset(unsigned Idx) { in reset()
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H A DSmallBitVector.h94 BitVector *getPointer() const { in getPointer()
96 return reinterpret_cast<BitVector *>(X); in getPointer()
105 void switchToLarge(BitVector *BV) { in switchToLarge()
149 switchToLarge(new BitVector(s, t));
157 switchToLarge(new BitVector(*RHS.getPointer())); in SmallBitVector()
337 BitVector *BV = new BitVector(N, t);
350 BitVector *BV = new BitVector(SmallSize); in reserve()
605 switchToLarge(new BitVector(*RHS.getPointer()));
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DGlobPattern.cpp27 static Expected<BitVector> expand(StringRef S, StringRef Original) { in expand()
28 BitVector BV(256, false); in expand()
67 static Expected<BitVector> scan(StringRef &S, StringRef Original) { in scan()
73 return BitVector(); in scan()
76 return BitVector(256, true); in scan()
88 Expected<BitVector> BV = expand(Chars.substr(1), Original); in scan()
101 BitVector BV(256, false); in scan()
135 Expected<BitVector> BV = scan(S, Original); in create()
154 bool GlobPattern::matchOne(ArrayRef<BitVector> Pats, StringRef S) const { in matchOne()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h67 BitVector KillRegUnits, DefRegUnits;
68 BitVector TmpRegUnits;
116 BitVector getRegsAvailable(const TargetRegisterClass *RC);
185 void setUsed(const BitVector &RegUnits) { in setUsed()
188 void setUnused(const BitVector &RegUnits) { in setUnused()
197 void addRegUnits(BitVector &BV, MCRegister Reg);
200 void removeRegUnits(BitVector &BV, MCRegister Reg);
207 BitVector &Candidates,
H A DLiveRangeCalc.h64 BitVector Seen;
77 using EntryInfoMap = DenseMap<LiveRange *, std::pair<BitVector, BitVector>>;
131 MachineBasicBlock &MBB, BitVector &DefOnEntry,
132 BitVector &UndefOnEntry);
H A DRDFRegisters.h130 const BitVector &getMaskUnits(RegisterId MaskId) const { in getMaskUnits()
134 const BitVector &getUnitAliases(uint32_t U) const { in getUnitAliases()
150 BitVector Units;
153 BitVector Regs;
179 return DenseMapInfo<BitVector>::isEqual(Units, A.Units);
199 return DenseMapInfo<BitVector>::getHashValue(Units); in hash()
245 BitVector Units;
H A DLiveRegUnits.h32 BitVector Units;
144 void addUnits(const BitVector &RegUnits) { in addUnits()
148 void removeUnits(const BitVector &RegUnits) { in removeUnits()
152 const BitVector &getBitVector() const { in getBitVector()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DStackLifetime.h47 BitVector Begin;
50 BitVector End;
53 BitVector LiveIn;
56 BitVector LiveOut;
65 BitVector Bits;
114 BitVector InterestingAllocas;
170 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
128 void expandReg(unsigned Reg, BitVector &Set) const;
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
130 BitVector &Uses) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs()
151 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg()
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses()
159 BitVector &Uses) const { in getDefsUses()
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H A DHexagonFrameLowering.h23 class BitVector; variable
79 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
128 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/
H A DGIMatchTree.h269 BitVector RemainingInstrNodes;
270 BitVector RemainingEdges;
271 BitVector RemainingPredicates;
274 std::vector<BitVector> UnsatisfiedPredDepsForPred;
279 BitVector TraversableEdges;
280 BitVector TestablePredicates;
334 iterator_range<llvm::BitVector::const_set_bits_iterator>
338 iterator_range<llvm::BitVector::const_set_bits_iterator>
342 iterator_range<llvm::BitVector::const_set_bits_iterator>
453 DenseMap<unsigned, BitVector> Partitions;
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H A DGIMatchTree.cpp86 RemainingInstrNodes(BitVector(MatchDag.getNumInstrNodes(), true)), in GIMatchTreeBuilderLeafInfo()
87 RemainingEdges(BitVector(MatchDag.getNumEdges(), true)), in GIMatchTreeBuilderLeafInfo()
88 RemainingPredicates(BitVector(MatchDag.getNumPredicates(), true)), in GIMatchTreeBuilderLeafInfo()
102 BitVector(PredicateDepIDs.size())); in GIMatchTreeBuilderLeafInfo()
397 BitVector TestedPredicatesForLeaf( in repartition()
469 BitVector Contents(Leaves.size()); in repartition()
493 BitVector Contents(Leaves.size()); in repartition()
510 BitVector Contents(Leaves.size()); in repartition()
522 BitVector Contents(Leaves.size()); in repartition()
537 BitVector PossibleLeaves = getPossibleLeavesForPartition(PartitionIdx); in applyForPartition()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DStackColoring.cpp420 BitVector Begin;
423 BitVector End;
426 BitVector LiveIn;
429 BitVector LiveOut;
461 BitVector InterestingSlots;
465 BitVector ConservativeSlots;
468 BitVector StoreSlots;
485 using BlockBitVecMap = DenseMap<const MachineBasicBlock *, BitVector>;
491 void dumpBV(const char *tag, const BitVector &BV) const;
566 const BitVector &BV) const { in dumpBV()
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H A DSpillPlacement.h37 class BitVector; variable
53 BitVector *ActiveNodes;
110 void prepare(BitVector &RegBundles);
H A DRegUsageInfoCollector.cpp61 static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
138 BitVector SavedRegs; in runOnMachineFunction()
141 const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); in runOnMachineFunction()
196 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { in computeCalleeSavedRegs()
H A DLiveRangeCalc.cpp125 MachineBasicBlock &MBB, BitVector &DefOnEntry, in isDefOnEntry()
126 BitVector &UndefOnEntry) { in isDefOnEntry()
301 std::make_pair(&LR, std::make_pair(BitVector(), BitVector()))); in findReachingDefs()
308 BitVector &DefOnEntry = Entry->second.first; in findReachingDefs()
309 BitVector &UndefOnEntry = Entry->second.second; in findReachingDefs()
438 BitVector DefBlocks(MF.getNumBlockIDs()); in isJointlyDominated()
H A DCFIInstrInserter.cpp82 BitVector IncomingCSRSaved;
84 BitVector OutgoingCSRSaved;
187 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); in calculateOutgoingCFAInfo()
267 BitVector::apply([](auto x, auto y, auto z) { return (x | y) & ~z; }, in calculateOutgoingCFAInfo()
297 BitVector SetDifference; in insertCFIInstrs()
349 BitVector::apply([](auto x, auto y) { return x & ~y; }, SetDifference, in insertCFIInstrs()
359 BitVector::apply([](auto x, auto y) { return x & ~y; }, SetDifference, in insertCFIInstrs()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Frontend/OpenMP/
H A DOMPContext.h148 BitVector RequiredTraits = BitVector(unsigned(TraitProperty::Last) + 1);
175 BitVector ActiveTraits = BitVector(unsigned(TraitProperty::Last) + 1);

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