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Searched refs:BaseReg (Results 1 – 25 of 80) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp384 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
393 if (BaseReg != 0) in optTwoAddrLEA()
394 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
406 if (DestReg != BaseReg) in optTwoAddrLEA()
407 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
412 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
417 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
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H A DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
84 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
293 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference()
295 BaseReg.getReg() == X86::RIP) in PrintLeaMemReference()
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
360 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference()
362 BaseReg.getReg() == X86::RIP) in PrintIntelMemReference()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
51 .addReg(BaseReg) in ReplaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
61 if (!BaseReg) { in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in ReplaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
72 RS->setRegUsed(BaseReg); in ReplaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in ReplaceFrameIndex()
94 .addReg(BaseReg, KillState) in ReplaceFrameIndex()
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H A DARCOptAddrMode.cpp90 MachineOperand &Incr, unsigned BaseReg);
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
143 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
219 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
231 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
240 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
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H A DThumb2InstrInfo.cpp278 Register BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
282 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
284 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
294 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
316 .addReg(BaseReg) in emitT2RegPlusImmediate()
328 .addReg(BaseReg) in emitT2RegPlusImmediate()
341 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
344 .addReg(BaseReg) in emitT2RegPlusImmediate()
347 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
351 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
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H A DARMBaseRegisterInfo.cpp660 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
661 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
663 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
669 return BaseReg; in materializeFrameBaseRegister()
672 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
691 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
694 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex()
701 Register BaseReg, in isFrameOffsetLegal() argument
742 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
H A DThumb2SizeReduction.cpp499 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
500 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
506 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
529 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
531 if (MI->getOperand(i).getReg() == BaseReg) in ReduceLoadStore()
537 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
538 if (BaseReg != ARM::SP) in ReduceLoadStore()
550 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
551 if (BaseReg == ARM::SP && in ReduceLoadStore()
556 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
406 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
424 BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset); in insertFrameReferenceRegisters()
426 LLVM_DEBUG(dbgs() << " into " << printReg(BaseReg, TRI) << '\n'); in insertFrameReferenceRegisters()
436 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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H A DImplicitNullChecks.cpp380 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local
385 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp()
391 if ((BaseReg && in isSuitableMemoryOp()
392 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
451 if (CalculateDisplacementFromAddrMode(BaseReg, 1)) in isSuitableMemoryOp()
461 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) || in isSuitableMemoryOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp66 SDValue BaseReg; member
93 return BaseType == Base::FrameIndexBase || BaseReg.getNode() != nullptr; in hasBase()
99 return BaseType == Base::RegBase && BaseReg.getNode() != nullptr; in hasBaseReg()
137 if (auto *RegNode = dyn_cast_or_null<RegisterSDNode>(BaseReg.getNode())) in isPCRelative()
144 BaseReg = Reg; in setBaseReg()
154 if (BaseReg.getNode()) in dump()
155 BaseReg.getNode()->dump(); in dump()
385 AM.BaseReg = N; in matchAddressBase()
460 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) { in matchAddressRecursively()
509 AM.BaseReg = N.getOperand(0); in matchADD()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp426 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon301d74170111::X86AsmParser::IntelExprStateMachine
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
459 unsigned getBaseReg() const { return BaseReg; } in getBaseReg()
655 if (!BaseReg) { in onPlus()
656 BaseReg = TmpReg; in onPlus()
716 if (!BaseReg) { in onMinus()
717 BaseReg = TmpReg; in onMinus()
964 if (!BaseReg) { in onRBrac()
965 BaseReg = TmpReg; in onRBrac()
1122 unsigned BaseReg, unsigned IndexReg,
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H A DX86Operand.h60 unsigned BaseReg; member
134 if (Mem.BaseReg) in print()
135 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
184 return Mem.BaseReg; in getMemBaseReg()
320 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
670 Res->Mem.BaseReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
702 Res->Mem.BaseReg = BaseReg;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp176 unsigned BaseReg, int Offset);
1238 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1267 BaseReg == getLdStBaseOp(MI).getReg() && getLdStOffsetOp(MI).isImm() && in findMatchingStore()
1282 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1533 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1602 if (BaseReg == MIBaseReg) { in findMatchingInsn()
1687 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1753 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1835 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1851 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
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H A DAArch64FalkorHWPFFix.cpp217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
652 LI.BaseReg = BaseReg; in getLoadInfo()
662 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
756 NewLdI.BaseReg = ScratchReg; in runOnLoop()
773 .addReg(LdI.BaseReg) in runOnLoop()
786 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
H A DAArch64StorePairSuppress.cpp156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
157 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
166 PrevBaseReg = BaseReg; in runOnMachineFunction()
H A DAArch64RegisterInfo.cpp536 Register BaseReg, in isFrameOffsetLegal() argument
558 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
559 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
562 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
567 return BaseReg; in materializeFrameBaseRegister()
570 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
584 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
H A DAArch64RegisterInfo.h108 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
112 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp131 unsigned BaseReg; member
173 return Mem.BaseReg; in getMemBaseReg()
616 Op->Mem.BaseReg = 0; in MorphToMemImm()
624 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
628 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
636 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
640 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
909 unsigned BaseReg = 0; in parseMemoryOperand() local
966 BaseReg = Op->getReg(); in parseMemoryOperand()
994 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp166 unsigned BaseReg = Base.getReg(); in is16BitMemOperand() local
169 if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0) in is16BitMemOperand()
171 if ((BaseReg != 0 && in is16BitMemOperand()
172 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) || in is16BitMemOperand()
183 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand() local
186 if ((BaseReg.getReg() != 0 && in is32BitMemOperand()
187 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in is32BitMemOperand()
191 if (BaseReg.getReg() == X86::EIP) { in is32BitMemOperand()
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand() local
208 if ((BaseReg.getReg() != 0 && in is64BitMemOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h66 StringRef BaseReg; member
72 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
82 bool hasBaseReg() const { return !BaseReg.empty(); } in hasBaseReg()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp270 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
277 setMemOp(IT, 1, MCOperand::createReg(BaseReg)); in generateLEATemplatesCommon()
286 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow); in generateLEATemplatesCommon()
296 CT.Config = formatv("{3}(%{0}, %{1}, {2})", RegInfo.getName(BaseReg), in generateLEATemplatesCommon()
334 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
339 State.getRATC().getRegister(BaseReg).aliasedBits(); in generateCodeTemplates()
394 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
398 State.getRATC().getRegister(BaseReg).aliasedBits()); in generateCodeTemplates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp1250 unsigned BaseReg = 0; in parseMEMOperand() local
1251 if (ParseRegister(BaseReg, S, E)) in parseMEMOperand()
1260 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset)) in parseMEMOperand()
1261 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset))); in parseMEMOperand()
1280 unsigned BaseReg = VE::NoRegister; in parseMEMAsOperand() local
1299 if (ParseRegister(BaseReg, S, E)) in parseMEMAsOperand()
1318 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1319 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset)) in parseMEMAsOperand()
1324 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
1332 if (ParseRegister(BaseReg, S, E)) in parseMEMAsOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h51 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
54 if (Op.isReg() && Op.getReg() == BaseReg) in isLDMBaseRegInList()

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