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Searched refs:BasePtrReg (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp738 Register BasePtrReg = in emitPrologue() local
823 .addReg(BasePtrReg); in emitPrologue()
858 .addReg(BasePtrReg) in emitPrologue()
875 .addReg(BasePtrReg) in emitPrologue()
933 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), BasePtrReg) in emitPrologue()
983 const Register BasePtrReg = in emitEpilogue() local
1003 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), BasePtrReg) in emitEpilogue()
1046 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), BasePtrReg) in emitEpilogue()
1054 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READLANE_B32), BasePtrReg) in emitEpilogue()
1251 Register BasePtrReg = RI->getBaseRegister(); in assignCalleeSavedSpillSlots() local
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H A DSIRegisterInfo.cpp566 MCRegister BasePtrReg = getBaseRegister(); in getReservedRegs() local
567 reserveRegisterTuples(Reserved, BasePtrReg); in getReservedRegs()
568 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
H A DAMDGPURegisterBankInfo.cpp1222 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad() local
1224 MRI.setType(BasePtrReg, PtrTy); in applyMappingLoad()