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Searched refs:BaseOpcode (Results 1 – 25 of 40) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp132 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
137 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
138 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
139 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
156 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
55 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
60 let PrimaryKey = ["BaseOpcode"];
173 MIMGBaseOpcode BaseOpcode;
182 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
186 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
218 let d16 = !if(BaseOpcode.HasD16, ?, 0);
228 let d16 = !if(BaseOpcode.HasD16, ?, 0);
239 let d16 = !if(BaseOpcode.HasD16, ?, 0);
256 let d16 = !if(BaseOpcode.HasD16, ?, 0);
[all …]
H A DAMDGPUInstrInfo.h52 unsigned BaseOpcode; member
79 const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
H A DAMDGPUInstructionSelector.cpp1469 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in selectImageIntrinsic() local
1470 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in selectImageIntrinsic()
1474 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode); in selectImageIntrinsic()
1476 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode); in selectImageIntrinsic()
1477 unsigned IntrOpcode = Intr->BaseOpcode; in selectImageIntrinsic()
1488 if (!BaseOpcode->Sampler) in selectImageIntrinsic()
1511 if (BaseOpcode->Atomic) { in selectImageIntrinsic()
1517 const bool Is64Bit = BaseOpcode->AtomicX2 ? in selectImageIntrinsic()
1521 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
1532 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in selectImageIntrinsic()
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H A DAMDGPULegalizerInfo.cpp4123 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in legalizeImageIntrinsic() local
4124 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in legalizeImageIntrinsic()
4142 if (!BaseOpcode->Atomic) { in legalizeImageIntrinsic()
4144 if (BaseOpcode->Gather4) { in legalizeImageIntrinsic()
4148 } else if (!IsTFE && !BaseOpcode->Store) { in legalizeImageIntrinsic()
4173 if (BaseOpcode->Atomic) { in legalizeImageIntrinsic()
4181 if (BaseOpcode->AtomicX2) { in legalizeImageIntrinsic()
4195 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode)) { in legalizeImageIntrinsic()
4218 if (AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode)) { in legalizeImageIntrinsic()
4232 if (BaseOpcode->Gradients && !ST.hasG16() && (IsA16 != IsG16)) { in legalizeImageIntrinsic()
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H A DSIISelLowering.cpp1045 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in getTgtMemIntrinsic() local
1046 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in getTgtMemIntrinsic()
1048 if (!BaseOpcode->Gather4) { in getTgtMemIntrinsic()
5964 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in lowerImage() local
5965 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in lowerImage()
5968 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode); in lowerImage()
5970 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode); in lowerImage()
5971 unsigned IntrOpcode = Intr->BaseOpcode; in lowerImage()
5989 if (BaseOpcode->Atomic) { in lowerImage()
5993 if (BaseOpcode->AtomicX2) { in lowerImage()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
297 let BaseOpcode = "c.f."#NAME;
302 let BaseOpcode = "c.un."#NAME;
307 let BaseOpcode = "c.eq."#NAME;
312 let BaseOpcode = "c.ueq."#NAME;
317 let BaseOpcode = "c.olt."#NAME;
321 let BaseOpcode = "c.ult."#NAME;
325 let BaseOpcode = "c.ole."#NAME;
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H A DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
80 string BaseOpcode = instr_asm;
97 string BaseOpcode = instr_asm;
115 string BaseOpcode = instr_asm;
131 string BaseOpcode = instr_asm;
145 string BaseOpcode = instr_asm;
171 string BaseOpcode = instr_asm;
H A DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
[all …]
H A DMipsInstrFPU.td288 let BaseOpcode = "c.f."#NAME;
293 let BaseOpcode = "c.un."#NAME;
298 let BaseOpcode = "c.eq."#NAME;
303 let BaseOpcode = "c.ueq."#NAME;
308 let BaseOpcode = "c.olt."#NAME;
312 let BaseOpcode = "c.ult."#NAME;
316 let BaseOpcode = "c.ole."#NAME;
320 let BaseOpcode = "c.ule."#NAME;
324 let BaseOpcode = "c.sf."#NAME;
329 let BaseOpcode = "c.ngle."#NAME;
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H A DMicroMips32r6InstrInfo.td614 string BaseOpcode = opstr;
649 string BaseOpcode = instr_asm;
664 string BaseOpcode = opstr;
677 string BaseOpcode = opstr;
688 string BaseOpcode = opstr;
700 string BaseOpcode = opstr;
722 string BaseOpcode = opstr;
735 string BaseOpcode = opstr;
744 string BaseOpcode = opstr;
765 string BaseOpcode = "ldc1";
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H A DMipsDSPInstrFormats.td13 // Instructions with the same BaseOpcode and isNVStore values form a row.
14 let RowFields = ["BaseOpcode"];
49 string BaseOpcode = opstr;
H A DMipsInstrFormats.td42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
119 string BaseOpcode = opstr;
H A DMips32r6InstrFormats.td17 // Instructions with the same BaseOpcode and isNVStore values form a row.
18 let RowFields = ["BaseOpcode"];
29 string BaseOpcode = opstr;
H A DMicroMipsInstrInfo.td217 let BaseOpcode = opstr;
228 let BaseOpcode = opstr;
270 string BaseOpcode = opstr;
286 string BaseOpcode = opstr;
592 let BaseOpcode = opstr;
597 let BaseOpcode = opstr;
604 let BaseOpcode = opstr;
611 let BaseOpcode = opstr;
H A DMicroMipsDSPInstrFormats.td13 string BaseOpcode = opstr;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1438 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1441 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1456 emitByte(BaseOpcode, OS); in encodeInstruction()
1465 emitByte(BaseOpcode + OpcodeOffset, OS); in encodeInstruction()
1477 emitByte(BaseOpcode, OS); in encodeInstruction()
1484 emitByte(BaseOpcode, OS); in encodeInstruction()
1492 emitByte(BaseOpcode, OS); in encodeInstruction()
1501 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), OS); in encodeInstruction()
1505 emitByte(BaseOpcode, OS); in encodeInstruction()
1521 emitByte(BaseOpcode, OS); in encodeInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagon.td162 // Instructions with the same BaseOpcode and isNVStore values form a row.
163 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
178 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
190 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
202 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
214 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
226 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
238 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
320 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
328 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
[all …]
H A DHexagonDepInstrInfo.td53 let BaseOpcode = "A2_add";
217 let BaseOpcode = "A2_addi";
303 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
356 let BaseOpcode = "A2_asrh";
430 let BaseOpcode = "A2_combinew";
588 let BaseOpcode = "A2_or";
632 let BaseOpcode = "A2_add";
649 let BaseOpcode = "A2_add";
664 let BaseOpcode = "A2_addi";
[all …]
H A DHexagonPseudo.td168 let BaseOpcode = "call";
200 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
298 isBarrier = 1, BaseOpcode = "JMPret" in {
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp138 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
140 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding, in getMIMGOpcode()
147 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
153 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()
158 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, in getAddrSizeMIMGOp() argument
161 unsigned AddrWords = BaseOpcode->NumExtraArgs; in getAddrSizeMIMGOp()
162 unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + in getAddrSizeMIMGOp()
163 (BaseOpcode->LodOrClampOrMip ? 1 : 0); in getAddrSizeMIMGOp()
174 if (BaseOpcode->Gradients) { in getAddrSizeMIMGOp()
175 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16) in getAddrSizeMIMGOp()
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H A DAMDGPUBaseInfo.h281 MIMGBaseOpcode BaseOpcode; member
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
351 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
357 uint16_t BaseOpcode; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrFormats.td113 string BaseOpcode = "";
408 let BaseOpcode = "ld_rs9";
419 let BaseOpcode = "ld_rs9";
445 let BaseOpcode = "ld_limm";
475 let BaseOpcode = "ld_rlimm";
499 let BaseOpcode = "st_rs9";
510 let BaseOpcode = "st_rs9";
535 let BaseOpcode = "st_limm";
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp720 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst() local
721 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
727 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
759 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()

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