| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch()
218 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && in runOnMachineFunction()
229 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg()) in runOnMachineFunction()
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| H A D | X86AsmPrinter.cpp | 289 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference()
329 PrintModifiedOperand(MI, OpNo + X86::AddrIndexReg, O, Modifier); in PrintLeaMemReference()
355 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference()
383 PrintOperand(MI, OpNo + X86::AddrIndexReg, O); in PrintIntelMemReference()
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| H A D | X86FixupLEAs.cpp | 374 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA()
471 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
506 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA()
558 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
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| H A D | X86OptimizeLEAs.cpp | 196 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey()
564 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
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| H A D | X86SpeculativeLoadHardening.cpp | 1340 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1414 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden()
1816 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
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| H A D | X86CallFrameOptimization.cpp | 431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
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| H A D | X86InstrInfo.h | 116 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
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| H A D | X86AvoidStoreForwardingBlocks.cpp | 317 const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
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| H A D | X86LoadValueInjectionLoadHardening.cpp | 789 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in instrUsesRegToAccessMemory()
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| H A D | X86InstrInfo.cpp | 681 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
684 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand()
1087 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
1088 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
1106 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
1107 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
3689 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
3754 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth()
6728 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg)) in areLoadsFromSameBasePtr()
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| H A D | X86MCInstLower.cpp | 384 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
408 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
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| H A D | X86FastISel.cpp | 228 X86::AddrIndexReg); in addFullAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 164 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
184 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand()
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand()
388 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte()
904 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
951 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
967 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
984 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1011 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix()
1262 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X in emitREXPrefix()
[all …]
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| H A D | X86IntelInstPrinter.cpp | 357 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference()
375 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
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| H A D | X86ATTInstPrinter.cpp | 399 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
423 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
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| H A D | X86BaseInfo.h | 34 AddrIndexReg = 2, enumerator
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| H A D | X86MCTargetDesc.cpp | 544 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 3790 MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg()); in validateInstruction()
3822 MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg()); in validateInstruction()
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