| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| H A D | bif_5_1_enum.h | 527 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | bif_5_0_enum.h | 37 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/ |
| H A D | smu_8_0_enum.h | 527 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | smu_7_1_0_enum.h | 80 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | smu_7_1_3_enum.h | 84 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | smu_7_1_1_enum.h | 87 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | smu_7_1_2_enum.h | 87 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| H A D | gmc_8_2_enum.h | 527 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | gmc_8_1_enum.h | 37 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| H A D | dce_8_0_enum.h | 37 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | dce_10_0_enum.h | 612 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_enum.h | 540 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | uvd_5_0_enum.h | 50 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_enum.h | 222 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | oss_3_0_enum.h | 336 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| H A D | oss_3_0_1_enum.h | 923 ARRAY_LINEAR_ALIGNED = 0x1, enumerator
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v6_0.c | 483 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); in gfx_v6_0_tiling_mode_table_init()
713 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v6_0_tiling_mode_table_init()
913 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); in gfx_v6_0_tiling_mode_table_init()
1137 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); in gfx_v6_0_tiling_mode_table_init()
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| H A D | amdgpu_gfx_v8_0.c | 2145 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2321 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2510 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2700 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2902 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
3100 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
3277 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
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| H A D | amdgpu_gfx_v7_0.c | 1091 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
1262 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
1444 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
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| H A D | sid.h | 1182 # define ARRAY_LINEAR_ALIGNED 1 macro
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_evergreen_cs.c | 316 case ARRAY_LINEAR_ALIGNED: in evergreen_surface_check()
338 case ARRAY_LINEAR_ALIGNED: in evergreen_surface_value_conv_check()
920 case ARRAY_LINEAR_ALIGNED: in evergreen_cs_track_validate_texture()
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| H A D | sid.h | 1184 # define ARRAY_LINEAR_ALIGNED 1 macro
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| H A D | cikd.h | 1222 # define ARRAY_LINEAR_ALIGNED 1 macro
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| H A D | radeon_cik.c | 2414 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2557 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2701 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2781 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2925 tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
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| H A D | evergreend.h | 2185 # define ARRAY_LINEAR_ALIGNED 1 macro
|