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Searched refs:ARC (Results 1 – 25 of 353) sorted by relevance

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/netbsd-src/external/gpl2/groff/dist/doc/
H A Dgrnexmpl.g3 ARC
41 ARC
51 ARC
101 ARC
135 ARC
151 ARC
161 ARC
194 ARC
228 ARC
337 ARC
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp66 AdjOp = Positive ? ARC::ADD_rru6 : ARC::SUB_rru6; in generateStackAdjustment()
68 AdjOp = Positive ? ARC::ADD_rrs12 : ARC::SUB_rrs12; in generateStackAdjustment()
70 AdjOp = Positive ? ARC::ADD_rrlimm : ARC::SUB_rrlimm; in generateStackAdjustment()
80 assert(Reg.getReg() >= ARC::R13 && Reg.getReg() <= ARC::R25 && in determineLastCalleeSave()
93 SavedRegs.set(ARC::BLINK); in determineCalleeSaves()
109 ScalarAlloc, ARC::SP); in adjustStackToMatchRecords()
137 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue()
139 Opc = ARC::SUB_rru6; in emitPrologue()
141 Opc = ARC::SUB_rrs12; in emitPrologue()
142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
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H A DARCRegisterInfo.cpp48 if (MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) { in ReplaceFrameIndex()
50 BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg) in ReplaceFrameIndex()
58 if (MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) { in ReplaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
74 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in ReplaceFrameIndex()
83 case ARC::LD_rs9: in ReplaceFrameIndex()
86 case ARC::LDH_rs9: in ReplaceFrameIndex()
87 case ARC::LDH_X_rs9: in ReplaceFrameIndex()
90 case ARC::LDB_rs9: in ReplaceFrameIndex()
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H A DARCExpandPseudos.cpp48 case ARC::ST_FAR: in getMappedOp()
49 return ARC::ST_rs9; in getMappedOp()
50 case ARC::STH_FAR: in getMappedOp()
51 return ARC::STH_rs9; in getMappedOp()
52 case ARC::STB_FAR: in getMappedOp()
53 return ARC::STB_rs9; in getMappedOp()
62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore()
64 isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in ExpandStore()
85 case ARC::ST_FAR: in runOnMachineFunction()
86 case ARC::STH_FAR: in runOnMachineFunction()
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H A DARCInstrInfo.cpp47 : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {} in ARCInstrInfo()
54 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 || in isLoad()
55 Opcode == ARC::LDB_rs9; in isLoad()
59 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 || in isStore()
60 Opcode == ARC::STB_rs9; in isStore()
137 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; } in isUncondBranchOpcode()
140 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p; in isCondBranchOpcode()
143 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; } in isJumpOpcode()
285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
287 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
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H A DARCBranchFinalize.cpp96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
103 return ARC::BRcc_rr; in getBRccForPseudo()
104 return ARC::BRcc_ru6; in getBRccForPseudo()
109 if (MI->getOpcode() == ARC::BRcc_rr_p) in getCmpForPseudo()
110 return ARC::CMP_rr; in getCmpForPseudo()
111 return ARC::CMP_ru6; in getCmpForPseudo()
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) in replaceWithCmpBcc()
H A DARCRegisterInfo.td1 //===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===//
10 // Declarations that describe the ARC register file
15 let Namespace = "ARC";
70 def GPR32: RegisterClass<"ARC", [i32], 32,
75 def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
77 def GPR_S : RegisterClass<"ARC", [i32], 8,
H A DARCCallingConv.td1 //===- ARCCallingConv.td - Calling Conventions for ARC -----*- tablegen -*-===//
8 // This describes the calling conventions for ARC architecture.
12 // ARC Return Value Calling Convention
25 // ARC Argument Calling Conventions
H A DARC.td1 //===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
22 def ARC : Target {
H A DCMakeLists.txt1 add_llvm_component_group(ARC)
3 set(LLVM_TARGET_DEFINITIONS ARC.td)
44 ARC
H A DARCISelLowering.cpp75 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
80 setStackPointerRegisterToSaveRestore(ARC::SP); in ARCTargetLowering()
289 StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, in LowerCall()
399 SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32); in lowerCallResult()
492 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
520 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments()
521 ARC::R4, ARC::R5, ARC::R6, ARC::R7}; in LowerCallArguments()
537 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
H A DARCISelDAGToDAG.cpp54 Reg = CurDAG->getRegister(ARC::STATUS32, MVT::i32); in SelectCMOVPred()
174 isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm, in Select()
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-arc.texi7 @node ARC-Dependent
8 @chapter ARC Dependent Features
13 @chapter ARC Dependent Features
18 @cindex ARC support
20 * ARC Options:: Options
21 * ARC Syntax:: Syntax
22 * ARC Directives:: ARC Machine Directives
23 * ARC Modifiers:: ARC Assembler Modifiers
24 * ARC Symbols:: ARC Pre-defined Symbols
25 * ARC Opcodes:: Opcodes
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/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-arc.texi7 @node ARC-Dependent
8 @chapter ARC Dependent Features
13 @chapter ARC Dependent Features
18 @cindex ARC support
20 * ARC Options:: Options
21 * ARC Syntax:: Syntax
22 * ARC Directives:: ARC Machine Directives
23 * ARC Modifiers:: ARC Assembler Modifiers
24 * ARC Symbols:: ARC Pre-defined Symbols
25 * ARC Opcodes:: Opcodes
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp114 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
115 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
116 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
117 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
118 ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
/netbsd-src/external/gpl3/binutils.old/dist/bfd/
H A Dcpu-arc.c29 #define ARC(mach, print_name, default_p, next) \ macro
49 ARC (bfd_mach_arc_arc600, "A6" , false, &arch_info_struct[1]),
50 ARC (bfd_mach_arc_arc601, "ARC601", false, &arch_info_struct[2]),
51 ARC (bfd_mach_arc_arc700, "ARC700", false, &arch_info_struct[3]),
52 ARC (bfd_mach_arc_arc700, "A7", false, &arch_info_struct[4]),
53 ARC (bfd_mach_arc_arcv2, "ARCv2", false, &arch_info_struct[5]),
54 ARC (bfd_mach_arc_arcv2, "EM", false, &arch_info_struct[6]),
55 ARC (bfd_mach_arc_arcv2, "HS", false, NULL),
59 ARC (bfd_mach_arc_arc600, "ARC600", true, &arch_info_struct[0]);
/netbsd-src/external/gpl3/binutils/dist/bfd/
H A Dcpu-arc.c29 #define ARC(mach, print_name, default_p, next) \ macro
49 ARC (bfd_mach_arc_arc600, "A6" , false, &arch_info_struct[1]),
50 ARC (bfd_mach_arc_arc601, "ARC601", false, &arch_info_struct[2]),
51 ARC (bfd_mach_arc_arc700, "ARC700", false, &arch_info_struct[3]),
52 ARC (bfd_mach_arc_arc700, "A7", false, &arch_info_struct[4]),
53 ARC (bfd_mach_arc_arcv2, "ARCv2", false, &arch_info_struct[5]),
54 ARC (bfd_mach_arc_arcv2, "EM", false, &arch_info_struct[6]),
55 ARC (bfd_mach_arc_arcv2, "HS", false, NULL),
59 ARC (bfd_mach_arc_arc600, "ARC600", true, &arch_info_struct[0]);
/netbsd-src/external/apache2/llvm/dist/clang/docs/
H A DAutomaticReferenceCounting.rst62 Objective-C Automatic Reference Counting (ARC)
83 The secondary purpose is to act as a rationale for why ARC was designed in this
184 ARC is under continual evolution, and this document must be updated as the
191 ARC applies to Objective-C pointer types, block pointer types, and
218 ARC may be explicitly enabled with the compiler flag ``-fobjc-arc``. It may
222 If ARC is enabled, ``__has_feature(objc_arc)`` will expand to 1 in the
232 the restrictions imposed on their use under ARC. Note in particular that it
247 ARC's semantics and restrictions.
251 We are not at liberty to require all code to be recompiled with ARC;
252 therefore, ARC must interoperate with Objective-C code which manages retains
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/
H A Darc-passes.def1 /* Description of target passes for ARC.
20 /* First target dependent ARC if-conversion pass. */
23 /* Second target dependent ARC if-conversion pass. */
H A Darc.opt1 ; Options for the Synopsys DesignWare ARC port of the compiler
210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
230 Enable generation of ARC SIMD instructions via target-specific builtins.
234 -mcpu=CPU Compile code for ARC variant CPU.
250 -mtune=TUNE Tune code for given ARC variant.
397 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
428 Enable double load/store instructions for ARC HS.
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arc/
H A Darc-passes.def1 /* Description of target passes for ARC.
20 /* First target dependent ARC if-conversion pass. */
23 /* Second target dependent ARC if-conversion pass. */
H A Darc.opt1 ; Options for the Synopsys DesignWare ARC port of the compiler
214 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
234 Enable generation of ARC SIMD instructions via target-specific builtins.
238 -mcpu=CPU Compile code for ARC variant CPU.
254 -mtune=TUNE Tune code for given ARC variant.
403 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
434 Enable double load/store instructions for ARC HS.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCMCTargetDesc.cpp45 InitARCMCRegisterInfo(X, ARC::BLINK); in createARCMCRegisterInfo()
60 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, ARC::SP, 0); in createARCMCAsmInfo()
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/arc/
H A Dlibgcc-excl.ver1 # Exclude libgcc.so symbols for the Synopsys DesignWare ARC CPU.
28 # Exclude various symbols which should not be visible in libgcc.so for ARC.
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/arc/
H A Dlibgcc-excl.ver1 # Exclude libgcc.so symbols for the Synopsys DesignWare ARC CPU.
28 # Exclude various symbols which should not be visible in libgcc.so for ARC.

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