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Searched refs:ADDI (Results 1 – 25 of 91) sorted by relevance

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/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativePPC_64.c54 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
72 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
89 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
95 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
105 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
222 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op()
236 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff))); in emit_single_op()
264 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff)); in emit_single_op()
H A DsljitNativePPC_32.c34 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
103 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op()
116 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff))); in emit_single_op()
141 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff)); in emit_single_op()
H A DsljitNativeARM_64.c69 #define ADDI 0x91000000 macro
577 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg)); in emit_op_imm()
581 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (imm << 10)); in emit_op_imm()
590 …return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22)… in emit_op_imm()
597 …FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22… in emit_op_imm()
598 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(dst) | ((imm & 0xfff) << 10)); in emit_op_imm()
825 return push_inst(compiler, ADDI | RD(dst) | RN(reg) | (value << 10)); in emit_set_delta()
827 return push_inst(compiler, ADDI | (1 << 22) | RD(dst) | RN(reg) | (value >> 2)); in emit_set_delta()
945 FAIL_IF(push_inst(compiler, ADDI | RD(other_r) | RN(other_r) | ((argw & 0xfff) << 10))); in getput_arg()
947 … FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(other_r) | RN(other_r) | ((argw >> 12) << 10))); in getput_arg()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp43 bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
90 if (LoADDI->getOpcode() != RISCV::ADDI || in INITIALIZE_PASS()
147 if (OffsetTail.getOpcode() == RISCV::ADDI) { in matchLargeOffset()
190 case RISCV::ADDI: { in detectAndFoldOffset()
H A DRISCVRegisterInfo.cpp239 if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) { in eliminateFrameIndex()
263 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg) in eliminateFrameIndex()
277 if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) { in eliminateFrameIndex()
292 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL) in eliminateFrameIndex()
H A DRISCVExpandPseudoInsts.cpp202 RISCV::ADDI); in expandLoadLocalAddress()
217 SecondOpcode = RISCV::ADDI; in expandLoadAddress()
238 RISCV::ADDI); in expandLoadTLSGDAddress()
H A DRISCVInstrInfo.td346 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
491 // ADDI isn't always rematerializable, but isReMaterializable will be used as
494 def ADDI : ALU_ri<0b000, "addi">;
659 def : InstAlias<"nop", (ADDI X0, X0, 0)>;
686 def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
802 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
902 def : PatGprSimm12<add, ADDI>;
944 (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
946 (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
960 (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
[all …]
H A DRISCVInstrInfo.cpp56 return MCInstBuilder(RISCV::ADDI) in getNop()
125 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
813 case RISCV::ADDI: in isAsCheapAsAMove()
830 case RISCV::ADDI: in isCopyInstrImpl()
1382 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N) in getVLENFactoredAmount()
H A DRISCVInstrInfoC.td760 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
806 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
807 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
822 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
824 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
910 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
H A DRISCVFrameLowering.cpp71 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
119 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSEpilogue()
264 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
H A DRISCVExpandAtomicPseudoInsts.cpp305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
444 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg) in expandAtomicMinMaxOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp33 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
73 Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeqImpl()
/netbsd-src/sys/lib/libkern/arch/hppa/
H A Dmilli.S618 ADDI 1,arg0,arg0
625 ADDI 3,arg0,arg0
632 ADDI 7,arg0,arg0
639 ADDI 15,arg0,arg0
647 ADDI 1,arg0,arg0
662 ADDI 1,arg0,arg0
672 ADDI 3,arg0,t1
679 ADDI 1,arg0,arg0
687 ADDI 1,arg0,arg0
698 ADDI 5,arg0,t1
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dnios2r1.h265 #define MATCH_R1_ADDI MATCH_R1_OP (ADDI)
393 #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0)
457 #define MATCH_R1_SUBI MATCH_R1_OP (ADDI)
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dnios2r1.h265 #define MATCH_R1_ADDI MATCH_R1_OP (ADDI)
393 #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0)
457 #define MATCH_R1_SUBI MATCH_R1_OP (ADDI)
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/xtensa/
H A Dconstraints.md74 "A signed 8-bit integer constant for use with ADDI instructions."
104 "An integer constant that can be used in ADDI.N instructions."
/netbsd-src/external/gpl3/gcc/dist/gcc/config/xtensa/
H A Dconstraints.md74 "A signed 8-bit integer constant for use with ADDI instructions."
104 "An integer constant that can be used in ADDI.N instructions."
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def35 FUSION_OP_SET(ADDI, ADDI8, ADDItocL), \
H A DPPCRegisterInfo.cpp107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
600 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
653 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
1420 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1450 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/or1k/
H A Dpredicates.md70 ;; Return true for relocations that must use MOVHI+ADDI
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-xtensa.texi589 @cindex @code{ADDI} instructions, relaxation
590 @cindex relaxation of @code{ADDI} instructions
591 The Xtensa @code{ADDI} instruction only allows immediate operands in the
593 sequences for the @code{ADDI} operation. First, if the
594 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
596 option is not available). If the @code{ADDI} immediate is outside of
598 @code{ADDMI} instruction or @code{ADDMI}/@code{ADDI} sequence will be
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-xtensa.texi589 @cindex @code{ADDI} instructions, relaxation
590 @cindex relaxation of @code{ADDI} instructions
591 The Xtensa @code{ADDI} instruction only allows immediate operands in the
593 sequences for the @code{ADDI} operation. First, if the
594 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
596 option is not available). If the @code{ADDI} immediate is outside of
598 @code{ADDMI} instruction or @code{ADDMI}/@code{ADDI} sequence will be
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/microblaze/
H A Dmoddi3.S92 ADDI r30,r30,1
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/microblaze/
H A Dmoddi3.S92 ADDI r30,r30,1

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