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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
16 bits <5> Vdd32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
28 bits <5> Rss32;
30 bits <5> Rt32;
32 bits <2> Pd4;
36 bits <11> Ii;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
H A DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
H A DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
H A DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
[all …]
H A DMicroMipsDSPInstrFormats.td24 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
36 class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
37 bits<5> rt;
38 bits<5> rs;
47 class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
48 bits<5> rt;
49 bits<5> rs;
[all …]
H A DMips32r6InstrFormats.td43 class OPGROUP<bits<6> Val> {
44 bits<6> Value = Val;
65 class OPCODE2<bits<2> Val> {
66 bits<2> Value = Val;
72 class OPCODE3<bits<3> Val> {
73 bits<3> Value = Val;
77 class OPCODE5<bits<5> Val> {
78 bits<5> Value = Val;
97 class OPCODE6<bits<6> Val> {
98 bits<6> Value = Val;
[all …]
H A DMipsDSPInstrFormats.td39 class Field6<bits<6> val> {
40 bits<6> V = val;
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
[all …]
H A DMips16InstrFormats.td58 field bits<16> Inst;
59 bits<5> Opcode = 0;
61 // Top 5 bits are the 'opcode' field
65 field bits<16> SoftFail = 0;
75 field bits<32> Inst;
78 field bits<32> SoftFail = 0;
102 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
106 bits<11> imm11;
117 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
121 bits<3> rx;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/netbsd-src/lib/libc/gdtoa/
H A Dstrtordd.c38 ULtodd(L, bits, expt, k) ULong *L; ULong *bits; Long expt; int k; in ULtodd() argument
40 ULtodd(ULong *L, ULong *bits, Long expt, int k)
52 L[_1] = (bits[1] >> 21 | bits[2] << 11) & (ULong)0xffffffffL;
53 L[_0] = (bits[2] >> 21) | (bits[3] << 11 & 0xfffff)
56 if (bits[1] &= 0x1fffff) {
57 i = hi0bits(bits[1]) - 11;
65 bits[1] = bits[1] << i | bits[0] >> (32-i);
66 bits[0] = bits[0] << i & (ULong)0xffffffffL;
69 else if (bits[0]) {
70 i = hi0bits(bits[0]) + 21;
[all …]
H A Dstrtopdd.c48 ULong bits[4]; local
62 rv = strtodg(s, sp, fpi, &expt, bits);
73 u->L[_1] = (bits[1] >> 21 | bits[2] << 11) & 0xffffffffL;
74 u->L[_0] = (bits[2] >> 21) | ((bits[3] << 11) & 0xfffff)
77 if (bits[1] &= 0x1fffff) {
78 i = hi0bits(bits[1]) - 11;
86 bits[1] = bits[1] << i | bits[0] >> (32-i);
87 bits[0] = bits[0] << i & 0xffffffffL;
90 else if (bits[0]) {
91 i = hi0bits(bits[0]) + 21;
[all …]
/netbsd-src/lib/libc/gdtoa/test/
H A Dxtest.c86 union { long double d; UShort bits[5]; } u, v[2]; in main() member
105 sscanf(s+1, "%hx %hx %hx %hx %hx", &u.bits[_0], in main()
106 &u.bits[_1], &u.bits[_2], &u.bits[_3], in main()
107 &u.bits[_4]); in main()
109 printf(" --> f = #%x %x %x %x %x\n", u.bits[_0], in main()
110 u.bits[_1], u.bits[_2], u.bits[_3], u.bits[_4]); in main()
115 i = strtorx(ibuf, &se, r, u.bits); in main()
116 if (r == 1 && (i != strtopx(ibuf, &se1, v[0].bits) || se1 != se in main()
117 || memcmp(u.bits, v[0].bits, 10))) in main()
122 u.bits[_0], u.bits[_1], u.bits[_2], in main()
[all …]
H A DQtest.c85 union { long double d; ULong bits[4]; } u, v[2], w; in main() member
87 w.bits[0] = w.bits[3] = 0; in main()
91 Ltest = sizeof(long double) == 16 && w.bits[0] && w.bits[3]; in main()
111 u.bits[_0] = (ULong)strtoul(s1 = s+1, &se, 16); in main()
113 u.bits[_1] = (ULong)strtoul(s1 = se, &se, 16); in main()
115 u.bits[_2] = (ULong)strtoul(s1 = se, &se, 16); in main()
117 u.bits[_3] = (ULong)strtoul(s1 = se, &se, 16); in main()
121 printf(" --> f = #%lx %lx %lx %lx\n", U u.bits[_0], in main()
122 U u.bits[_1], U u.bits[_2], U u.bits[_3]); in main()
127 i = strtorQ(ibuf, &se, r, u.bits); in main()
[all …]
H A DxLtest.c84 union { long double d; ULong bits[3]; } u, v[2]; in main() member
105 u.bits[_0] = (ULong)strtoul(s1 = s+1, &se, 16); in main()
107 u.bits[_1] = (ULong)strtoul(s1=se, &se, 16); in main()
109 u.bits[_2] = (ULong)strtoul(s1=se, &se, 16); in main()
112 printf(" --> f = #%lx %lx %lx\n", U u.bits[_0], in main()
113 U u.bits[_1], U u.bits[_2]); in main()
118 i = strtorxL(ibuf, &se, r, u.bits); in main()
119 if (r == 1 && (i != strtopxL(ibuf, &se1, v[0].bits) || se1 != se in main()
120 || memcmp(u.bits, v[0].bits, 12))) in main()
125 U u.bits[_0], U u.bits[_1], U u.bits[_2]); in main()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
41 bits<1> XFormMemOp = 0;
45 bits<1> Prefixed = 0;
58 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dtegra124-peripherals-opp.dtsi9 opp-hz = /bits/ 64 <12750000>;
15 opp-hz = /bits/ 64 <12750000>;
21 opp-hz = /bits/ 64 <12750000>;
27 opp-hz = /bits/ 64 <12750000>;
33 opp-hz = /bits/ 64 <20400000>;
39 opp-hz = /bits/ 64 <20400000>;
45 opp-hz = /bits/ 64 <20400000>;
51 opp-hz = /bits/ 64 <20400000>;
57 opp-hz = /bits/ 64 <40800000>;
63 opp-hz = /bits/ 64 <40800000>;
[all …]
H A Dtegra30-peripherals-opp.dtsi9 opp-hz = /bits/ 64 <12750000>;
15 opp-hz = /bits/ 64 <12750000>;
21 opp-hz = /bits/ 64 <12750000>;
27 opp-hz = /bits/ 64 <25500000>;
33 opp-hz = /bits/ 64 <25500000>;
39 opp-hz = /bits/ 64 <25500000>;
45 opp-hz = /bits/ 64 <27000000>;
51 opp-hz = /bits/ 64 <27000000>;
57 opp-hz = /bits/ 64 <27000000>;
63 opp-hz = /bits/ 64 <51000000>;
[all …]
/netbsd-src/sys/fs/nfs/common/
H A Dnfs.h368 u_int32_t bits[NFSATTRBIT_MAXWORDS]; member
372 (b)->bits[0] = 0; \
373 (b)->bits[1] = 0; \
374 (b)->bits[2] = 0; \
378 (t)->bits[0] = (f)->bits[0]; \
379 (t)->bits[1] = (f)->bits[1]; \
380 (t)->bits[2] = (f)->bits[2]; \
384 (b)->bits[0] = NFSATTRBIT_SUPP0; \
385 (b)->bits[1] = (NFSATTRBIT_SUPP1 | NFSATTRBIT_SUPPSETONLY); \
386 (b)->bits[2] = NFSATTRBIT_SUPP2; \
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrFormats.td25 field bits<64> Inst;
30 bits<8> op;
38 bits<1> VE_Vector = 0;
39 bits<1> VE_VLInUse = 0;
40 bits<3> VE_VLIndex = 0;
41 bits<1> VE_VLWithMask = 0;
58 field bits<64> SoftFail = 0;
68 class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
70 bits<1> cx = 0;
71 bits<7> sx;
[all …]
/netbsd-src/sys/arch/ia64/disasm/
H A Ddisasm_extract.c99 uint64_t bits = i->i_bits; in asm_brhint() local
101 switch (FIELD(bits, 33, 2)) { /* bwh */ in asm_brhint()
116 if (FIELD(bits, 12, 1)) /* ph */ in asm_brhint()
121 if (FIELD(bits, 35, 1)) /* dh */ in asm_brhint()
130 uint64_t bits = i->i_bits; in asm_brphint() local
132 switch (FIELD(bits, 3, 2)) { /* ipwh, indwh */ in asm_brphint()
147 if (FIELD(bits, 5, 1)) /* ph */ in asm_brphint()
152 switch (FIELD(bits, 0, 3)) { /* pvec */ in asm_brphint()
179 if (FIELD(bits, 35, 1)) /* ih */ in asm_brphint()
1815 operand(struct asm_inst *i, int op, enum asm_oper_type ot, uint64_t bits, in operand() argument
[all …]
/netbsd-src/tests/usr.bin/xlint/lint1/
H A Dmsg_166.c34 struct bit_set bits; in example() local
38 bits.minus_1_to_0 = -2; in example()
39 bits.minus_1_to_0 = -1; in example()
40 bits.minus_1_to_0 = 0; in example()
42 bits.minus_1_to_0 = 1; in example()
44 bits.minus_1_to_0 = 2; in example()
47 bits.minus_8_to_7 = -9; in example()
48 bits.minus_8_to_7 = -8; in example()
49 bits.minus_8_to_7 = 7; in example()
51 bits.minus_8_to_7 = 8; in example()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
24 bits<2> Opcode = 0;
36 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
39 bits<5> rs1;
40 bits<5> rs2;
49 // is responsible for setting the appropriate bits in the Inst field.
50 // The bits Inst{6-2} must be set for each instruction.
51 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
54 bits<10> imm;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td12 field bits<32> Inst;
17 bits<2> op;
18 let Inst{31-30} = op; // Top two bits are the 'op' field
26 field bits<32> SoftFail = 0;
39 bits<3> op2;
40 bits<22> imm22;
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
51 bits<5> rd;
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
61 bits<4> cond;
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-a311d.dtsi15 opp-hz = /bits/ 64 <100000000>;
20 opp-hz = /bits/ 64 <250000000>;
25 opp-hz = /bits/ 64 <500000000>;
30 opp-hz = /bits/ 64 <667000000>;
35 opp-hz = /bits/ 64 <1000000000>;
40 opp-hz = /bits/ 64 <1200000000>;
45 opp-hz = /bits/ 64 <1398000000>;
50 opp-hz = /bits/ 64 <1512000000>;
55 opp-hz = /bits/ 64 <1608000000>;
60 opp-hz = /bits/ 64 <1704000000>;
[all …]

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