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/minix3/external/bsd/llvm/dist/llvm/test/MC/AArch64/
H A Darm64-verbose-vector-case.s3 pmull v8.8h, v8.8b, v8.8b
4 pmull2 v8.8h, v8.16b, v8.16b
5 pmull v8.1q, v8.1d, v8.1d
6 pmull2 v8.1q, v8.2d, v8.2d
12 pmull v8.8H, v8.8B, v8.8B
13 pmull2 v8.8H, v8.16B, v8.16B
14 pmull v8.1Q, v8.1D, v8.1D
15 pmull2 v8.1Q, v8.2D, v8.2D
H A Dneon-simd-misc.s11 rev64 v6.4s, v8.4s
44 saddlp v8.4h, v5.8b
62 uaddlp v8.4h, v5.8b
80 sadalp v8.4h, v5.8b
98 uadalp v8.4h, v5.8b
117 suqadd v6.4s, v8.4s
118 suqadd v6.2d, v8.2d
137 usqadd v6.4s, v8.4s
138 usqadd v6.2d, v8.2d
157 sqabs v6.4s, v8.4s
[all …]
H A Dneon-compare-instructions.s10 cmeq v1.16b, v31.16b, v8.16b
14 cmeq v9.4s, v7.4s, v8.4s
32 cmhs v1.16b, v31.16b, v8.16b
36 cmhs v9.4s, v7.4s, v8.4s
40 cmls v1.16b, v8.16b, v31.16b
44 cmls v9.4s, v8.4s, v7.4s
69 cmge v1.16b, v31.16b, v8.16b
73 cmge v9.4s, v7.4s, v8.4s
77 cmle v1.16b, v8.16b, v31.16b
81 cmle v9.4s, v8.4s, v7.4s
[all …]
H A Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
90 st1.2d {v7, v8}, [x10]
103 ; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
182 ; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
270 ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
285 ; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
1031 ld4r.16b {v5, v6, v7, v8}, [x2], #4
1032 ld4r.4h {v6, v7, v8, v9}, [x2], #8
[all …]
H A Darm64-advsimd.s128 dup v6.2s, v8.s[1]
144 ; CHECK: dup.2s v6, v8[1] ; encoding: [0x06,0x05,0x0c,0x0e]
260 mov v8.s[1], w3
267 mov.b v8[1], v15[1]
271 mov v8.h[7], v17.h[3]
279 ; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]
285 ; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]
288 ; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]
511 shll2.8h v7, v8, #8
561 ; CHECK: shll2.8h v7, v8, #8 ; encoding: [0x07,0x39,0x21,0x6e]
[all …]
H A Dneon-2velem.s11 mla v3.4s, v8.4s, v2.s[1]
12 mla v3.4s, v8.4s, v22.s[3]
31 mls v3.4s, v8.4s, v2.s[1]
32 mls v3.4s, v8.4s, v22.s[3]
51 fmla v3.4s, v8.4s, v2.s[1]
52 fmla v3.4s, v8.4s, v22.s[3]
65 fmls v3.4s, v8.4s, v2.s[1]
66 fmls v3.4s, v8.4s, v22.s[3]
H A Dneon-facge-facgt.s28 facgt v3.2s, v8.2s, v12.2s
31 faclt v3.2s, v12.2s, v8.2s
H A Dneon-diagnostics.s319 sabd v0.4h, v1.8h, v8.8h
563 fcmge v3.8b, v8.2s, v12.2s
699 fcmge v3.8b, v8.2s, #0.0
747 fcmge v3.8b, v8.2s, #0.0
3021 fmla v3.4s, v8.4s, v2.s[4]
3022 fmla v3.4s, v8.4s, v22.s[4]
3055 fmls v3.4s, v8.4s, v2.s[4]
3056 fmls v3.4s, v8.4s, v22.s[4]
5242 rev64 v6.2d, v8.2d
5285 saddlp v8.8b, v5.8b
[all …]
H A Dneon-frsqrt-frecp.s20 frecps v3.2s, v8.2s, v12.2s
H A Dneon-max-min.s72 fmax v7.2d, v8.2d, v25.2d
94 fmaxnm v7.2d, v8.2d, v25.2d
H A Dneon-max-min-pairwise.s72 fmaxp v7.2d, v8.2d, v25.2d
94 fmaxnmp v7.2d, v8.2d, v25.2d
/minix3/minix/drivers/bus/ti1225/
H A Dti1225.c141 u8_t v8; in hw_init() local
170 v8= pci_attr_r8(devind, TI_PCI_BUS_NR); in hw_init()
171 printf("ti1225: PCI bus number %d\n", v8); in hw_init()
173 v8= pci_attr_r8(devind, TI_CB_BUS_NR); in hw_init()
174 pp->p_cb_busnr= v8; in hw_init()
177 printf("ti1225: CardBus bus number %d\n", v8); in hw_init()
178 v8= pci_attr_r8(devind, TI_SO_BUS_NR); in hw_init()
179 printf("ti1225: Subordinate bus number %d\n", v8); in hw_init()
225 v8= pci_attr_r8(devind, TI_CARD_CTRL); in hw_init()
226 printf("ti1225: Card Control 0x%02x\n", v8); in hw_init()
[all …]
/minix3/external/bsd/llvm/dist/clang/test/Sema/
H A Daltivec-init.c4 typedef short v8 __attribute((vector_size(16)));
6 v8 foo(void) { in foo()
7 v8 a; in foo()
9 a = (v8){4, 2}; in foo()
24 return (v8){0, 1, 2, 3, 1, 2, 3, 4}; in foo()
/minix3/external/bsd/llvm/dist/clang/test/CXX/class/class.mem/
H A Dp1.cpp59 void v8();
60 int v8(int); //expected-note{{previous declaration is here}}
61 int v8; //expected-error{{duplicate member 'v8'}} member
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/
H A Darm64-copy-tuple.ll19 …tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
22 …tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
36 …tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
39 …tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
53 …tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{…
56 …tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
70 …tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~…
73 …tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{…
90 …tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},…
93 …tail call void asm sideeffect "", "~{v0},~{v1},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},…
[all …]
H A Darm64-anyregcc-crash.ll6 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
12 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
/minix3/external/bsd/llvm/dist/llvm/utils/unittest/googletest/include/gtest/
H A Dgtest-param-test.h396 T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8) { in Values() argument
398 v5, v6, v7, v8); in Values()
404 T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9) { in Values() argument
406 v4, v5, v6, v7, v8, v9); in Values()
412 T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, T10 v10) { in Values() argument
414 v2, v3, v4, v5, v6, v7, v8, v9, v10); in Values()
421 T11> Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, in Values() argument
424 T11>(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11); in Values()
431 T12> Values(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, in Values() argument
434 T12>(v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12); in Values()
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A Danyregcc-crash.ll7 i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
12 i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12,
/minix3/external/bsd/llvm/dist/llvm/test/TableGen/
H A DTwoLevelName.td18 defm v8#NAME# : OT1<!strconcat( "v8", ss), 8, w>;
/minix3/external/bsd/llvm/dist/clang/test/CodeGen/
H A Dppc64le-aggregates.c135 struct v8 { vector int v[8]; }; argument
163 struct v8 func_v8(struct v8 x) { return x; } in func_v8()
219 struct v8 global_v8;
H A Dvector-alignment.c25 double __attribute__((vector_size(32), aligned(64))) v8; variable
/minix3/external/bsd/llvm/dist/llvm/test/MC/ARM/
H A Dbasic-arm-instructions-v8.s20 @ DMB (v8 barriers)
37 @ DSB (v8 barriers)
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/PowerPC/
H A Dppc64-anyregcc-crash.ll6 define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
12 i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
/minix3/external/bsd/llvm/dist/llvm/test/Transforms/LoopVectorize/
H A Dif-pred-stores.ll12 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
14 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
50 ; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[v4]], true
51 ; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]]
/minix3/external/bsd/llvm/dist/llvm/utils/unittest/googletest/include/gtest/internal/
H A Dgtest-param-util-generated.h231 T8 v8) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7), in ValueArray8() argument
232 v8_(v8) {} in ValueArray8()
258 ValueArray9(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, in ValueArray9() argument
260 v8_(v8), v9_(v9) {} in ValueArray9()
287 ValueArray10(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, in ValueArray10() argument
289 v8_(v8), v9_(v9), v10_(v10) {} in ValueArray10()
318 ValueArray11(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, in ValueArray11() argument
320 v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11) {} in ValueArray11()
350 ValueArray12(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9, in ValueArray12() argument
352 v6_(v6), v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11), v12_(v12) {} in ValueArray12()
[all …]

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