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Searched refs:res11 (Results 1 – 11 of 11) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/R600/
H A Dllvm.SI.imageload.ll40 %res11 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11,
59 %t12 = extractelement <4 x i32> %res11, i32 0
60 %t13 = extractelement <4 x i32> %res11, i32 1
61 %t14 = extractelement <4 x i32> %res11, i32 2
H A Dllvm.SI.resinfo.ll33 %res11 = call <4 x i32> @llvm.SI.resinfo(i32 %a11, <32 x i8> undef, i32 11)
61 %t12 = extractelement <4 x i32> %res11, i32 0
62 %t13 = extractelement <4 x i32> %res11, i32 1
63 %t14 = extractelement <4 x i32> %res11, i32 2
H A Dllvm.SI.sampled.ll58 %res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11,
92 %t12 = extractelement <4 x float> %res11, i32 0
93 %t13 = extractelement <4 x float> %res11, i32 1
94 %t14 = extractelement <4 x float> %res11, i32 2
H A Dllvm.AMDGPU.tex.ll32 %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
33 %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res11, i32 0, i32 0, i32 12)
H A Dllvm.SI.sample.ll58 %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
92 %t12 = extractelement <4 x float> %res11, i32 0
93 %t13 = extractelement <4 x float> %res11, i32 1
94 %t14 = extractelement <4 x float> %res11, i32 2
H A Dfetch-limits.r700+.ll49 %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1)
60 %f = fadd <4 x float> %res10, %res11
/minix3/external/bsd/llvm/dist/llvm/test/Bitcode/
H A DmiscInstructions.3.2.ll99 ; CHECK-NEXT: %res11 = icmp eq i32* %ptr1, %ptr2
100 %res11 = icmp eq i32* %ptr1, %ptr2
141 ; CHECK-NEXT: %res11 = fcmp ord float %x1, %x2
142 %res11 = fcmp ord float %x1, %x2
H A DmemInstructions.3.2.ll60 ; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1
61 %res11 = load i8* %ptr1, align 1, !invariant.load !1
116 ; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
117 %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
270 ; CHECK-NEXT: %res11 = extractvalue { i32, i1 } [[TMP]], 0
271 %res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
/minix3/external/bsd/llvm/dist/clang/test/SemaCXX/
H A Daltivec.cpp30 int res11[vec_step(vui) == 4 ? 1 : -1]; in test_vec_step() local
/minix3/external/bsd/llvm/dist/clang/test/SemaOpenCL/
H A Dvec_step.cl26 int res11[vec_step(int16) == 16 ? 1 : -1];
/minix3/sys/dev/pci/
H A Dmlyreg.h262 u_int8_t res11:1; /* N/A */ member
579 u_int8_t res11:6; /* N/A */ member
810 u_int8_t res11[256]; member