Home
last modified time | relevance | path

Searched refs:Writes (Results 1 – 16 of 16) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp386 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
390 findRWs(WriteDefs, Writes, false); in findRWs()
512 IdxVec Writes, Reads; in collectSchedClasses() local
514 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
519 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses()
553 if (!SC.Writes.empty()) { in collectSchedClasses()
556 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI) in collectSchedClasses()
569 IdxVec Writes; in collectSchedClasses() local
572 Writes, Reads); in collectSchedClasses()
573 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) in collectSchedClasses()
[all …]
H A DCodeGenSchedule.h132 IdxVec Writes; member
148 return ItinClassDef == IC && Writes == W && Reads == R; in isKeyEqual()
360 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
372 const IdxVec &Writes,
418 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
H A DSubtargetEmitter.cpp883 IdxVec Writes = SCI->Writes; in GenSchedClassTables() local
898 Writes.clear(); in GenSchedClassTables()
901 Writes, Reads); in GenSchedClassTables()
904 if (Writes.empty()) { in GenSchedClassTables()
912 Writes, Reads); in GenSchedClassTables()
916 if (Writes.empty()) { in GenSchedClassTables()
926 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) { in GenSchedClassTables()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h159 bool Writes; member
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA9.td1883 list <WriteSequence> Writes = writes;
2087 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2088 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2089 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2090 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2091 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2092 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2093 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2094 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2192 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp274 RI.Writes = true; in analyzeVirtReg()
H A DInlineSpiller.cpp1277 if (RI.Writes) { in spillAroundUses()
1320 if (RI.Writes) in spillAroundUses()
H A DRegisterCoalescer.cpp1134 bool Reads, Writes; in updateRegDefsUses() local
1135 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); in updateRegDefsUses()
/minix3/crypto/external/bsd/openssl/dist/doc/crypto/
H A DBIO_s_mem.pod73 Writes to memory BIOs will always succeed if memory is available: that is
H A DBIO_s_bio.pod84 length of data that can be currently written to the BIO. Writes larger than this
/minix3/crypto/external/bsd/heimdal/dist/kadmin/
H A Dkadmin-commands.in69 help = "Writes the Kerberos master key to a file used by the KDC. \nLocal (-l) mode only."
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSchedule.td225 list<SchedWrite> Writes = writes;
309 // to implement pipeline bypass. The Writes list may be empty to
/minix3/external/bsd/bind/dist/contrib/dlz/example/
H A DREADME100 Writes the specified string to the named log, at the specified
/minix3/minix/servers/vfs/
H A DREADME525 are filp_count and filp_pos. Writes to and reads from filp object must be
/minix3/games/fortune/datfiles/
H A Dlimerick-o.real608 Writes to say she believes she's been hexed:
/minix3/external/bsd/llvm/dist/llvm/docs/
H A DLangRef.rst9383 Writes a vector to memory according to the provided mask. The mask holds a bit for each vector lane…