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Searched refs:TargetRegisterClass (Results 1 – 25 of 199) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h36 class TargetRegisterClass {
41 typedef const TargetRegisterClass* const * sc_iterator;
122 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
128 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
135 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
225 typedef const TargetRegisterClass * const * regclass_iterator;
312 const TargetRegisterClass *
317 const TargetRegisterClass *
318 getAllocatableClass(const TargetRegisterClass *RC) const;
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterInfo.h70 const TargetRegisterClass *
71 getMatchingSuperRegClass(const TargetRegisterClass *A,
72 const TargetRegisterClass *B,
75 const TargetRegisterClass *
76 getSubClassWithSubReg(const TargetRegisterClass *RC,
79 const TargetRegisterClass*
80 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
84 const TargetRegisterClass *
91 const TargetRegisterClass *
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIRegisterInfo.h41 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
47 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
50 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
66 bool hasVGPRs(const TargetRegisterClass *RC) const;
69 const TargetRegisterClass *getEquivalentVGPRClass(
70 const TargetRegisterClass *SRC) const;
75 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
81 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
119 const TargetRegisterClass *RC) const;
H A DSIFixSGPRCopies.cpp88 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
92 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
134 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses( in inferRegClassFromUses()
140 const TargetRegisterClass *RC in inferRegClassFromUses()
160 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef( in inferRegClassFromDef()
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef()
186 const TargetRegisterClass *DstRC in isVGPRToSGPRCopy()
191 const TargetRegisterClass *SrcRC; in isVGPRToSGPRCopy()
230 const TargetRegisterClass *RC in runOnMachineFunction()
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction()
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H A DSIInstrInfo.h32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
45 const TargetRegisterClass *RC,
102 const TargetRegisterClass *RC,
108 const TargetRegisterClass *RC,
116 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
137 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
249 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
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H A DSIRegisterInfo.cpp332 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( in getCFGStructurizerRegClass()
344 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { in getPhysRegClass()
347 static const TargetRegisterClass *BaseClasses[] = { in getPhysRegClass()
360 for (const TargetRegisterClass *BaseClass : BaseClasses) { in getPhysRegClass()
368 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs()
377 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass( in getEquivalentVGPRClass()
378 const TargetRegisterClass *SRC) const { in getEquivalentVGPRClass()
397 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass()
398 const TargetRegisterClass *RC, unsigned SubIdx) const { in getSubRegClass()
412 const TargetRegisterClass *SubRC, in getPhysRegSubReg()
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H A DR600RegisterInfo.h38 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
41 getRegClassWeight(const TargetRegisterClass *RC) const override;
H A DR600RegisterInfo.cpp47 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), in getReservedRegs()
65 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( in getCFGStructurizerRegClass()
74 const TargetRegisterClass *RC) const { in getRegClassWeight()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp87 const TargetRegisterClass *
88 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
98 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); in getAllocatableClass()
111 const TargetRegisterClass *
117 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
119 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass()
132 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
140 const TargetRegisterClass *RC) const { in getAllocatableSet()
144 const TargetRegisterClass *SubClass = getAllocatableClass(RC); in getAllocatableSet()
162 const TargetRegisterClass *firstCommonClass(const uint32_t *A, in firstCommonClass()
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H A DCriticalAntiDepBreaker.cpp64 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
79 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
109 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
116 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
178 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
188 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
197 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
198 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
203 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) in PrescanInstruction()
217 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) { in PrescanInstruction()
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H A DRegisterCoalescer.h22 class TargetRegisterClass; variable
57 const TargetRegisterClass *NewRC;
112 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
H A DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
69 const TargetRegisterClass *OldRC = S2RCMap[Slot]; in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print()
H A DMachineRegisterInfo.cpp41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass()
46 const TargetRegisterClass *
48 const TargetRegisterClass *RC, in constrainRegClass()
50 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
53 const TargetRegisterClass *NewRC = in constrainRegClass()
66 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
67 const TargetRegisterClass *NewRC = in recomputeRegClass()
92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
400 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h67 void compute(const TargetRegisterClass *RC) const;
70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
H A DRegisterScavenging.h29 class TargetRegisterClass; variable
118 BitVector getRegsAvailable(const TargetRegisterClass *RC);
122 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
151 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
153 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
H A DLiveStackAnalysis.h40 std::map<int, const TargetRegisterClass*> S2RCMap;
57 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
77 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
79 std::map<int, const TargetRegisterClass*>::const_iterator in getIntervalRegClass()
H A DFastISel.h384 const TargetRegisterClass *RC);
389 const TargetRegisterClass *RC, unsigned Op0,
395 const TargetRegisterClass *RC, unsigned Op0,
401 const TargetRegisterClass *RC, unsigned Op0,
408 const TargetRegisterClass *RC, unsigned Op0,
414 const TargetRegisterClass *RC, unsigned Op0,
420 const TargetRegisterClass *RC, unsigned Op0,
426 const TargetRegisterClass *RC, unsigned Op0,
433 const TargetRegisterClass *RC, unsigned Op0,
440 const TargetRegisterClass *RC, uint64_t Imm);
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h120 const TargetRegisterClass *
123 const TargetRegisterClass *
124 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
126 const TargetRegisterClass *
127 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
129 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
141 bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
191 const TargetRegisterClass *SrcRC,
193 const TargetRegisterClass *DstRC,
195 const TargetRegisterClass *NewRC) const override;
H A DThumb1RegisterInfo.h29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
32 const TargetRegisterClass *
55 const TargetRegisterClass *RC,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h26 class TargetRegisterClass; variable
65 const TargetRegisterClass *
68 const TargetRegisterClass *
69 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
95 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h37 const TargetRegisterClass *
40 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
43 const TargetRegisterClass*
44 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.h45 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
48 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
H A DMipsMachineFunction.cpp83 const TargetRegisterClass *RC = in getGlobalBaseReg()
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg()
105 const TargetRegisterClass *RC = ST.isABI_N64() ? in createEhDataRegsFI()
136 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
H A DMipsInstrInfo.h93 const TargetRegisterClass *RC, in storeRegToStackSlot()
101 const TargetRegisterClass *RC, in loadRegFromStackSlot()
109 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot()
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot()
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot()

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