| /minix3/external/bsd/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 51 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
66 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
77 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
88 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
99 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
102 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
105 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
115 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
120 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 159 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
193 SDValue Src1, SDValue Src2, SDValue Size, in EmitTargetCodeForMemcmp() argument
199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
249 SDValue Src1, SDValue Src2, in EmitTargetCodeForStrcmp() argument
253 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
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| H A D | SystemZSelectionDAGInfo.h | 42 SDValue Src1, SDValue Src2, SDValue Size,
60 SDValue Src1, SDValue Src2,
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| H A D | SystemZISelLowering.cpp | 2227 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
2234 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_OP()
2236 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType()); in lowerATOMIC_LOAD_OP()
2260 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
2264 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
2269 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
2294 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
2296 SDLoc DL(Src2); in lowerATOMIC_LOAD_SUB()
2298 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_SUB()
2307 Src2); in lowerATOMIC_LOAD_SUB()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 159 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() local
163 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
176 MachineOperand &Src2 = MI->getOperand(2); in runOnMachineFunction() local
177 if (Src2.getImm() != 32) in runOnMachineFunction()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | SIShrinkInstructions.cpp | 89 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
91 if (Src2) in canShrink()
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| H A D | SIInstrInfo.cpp | 1233 const MachineOperand &Src2 = MI->getOperand(Src2Idx); in verifyInstruction() local
1234 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { in verifyInstruction()
1236 !compareMachineOp(Src0, Src2)) { in verifyInstruction()
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| H A D | EvergreenInstructions.td | 269 // Src2 = Width
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| H A D | SIInstrInfo.td | 617 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
620 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 308 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM() local
312 .addOperand(Src2); in processInstructionForSLM()
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| H A D | X86InstrInfo.cpp | 2187 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddressWithLEA() local
2191 if (Src == Src2) { in convertToThreeAddressWithLEA()
2206 .addReg(Src2, getKillRegState(isKill2)); in convertToThreeAddressWithLEA()
2210 LV->replaceKillInstruction(Src2, MI, InsMI2); in convertToThreeAddressWithLEA()
2403 const MachineOperand &Src2 = MI->getOperand(2); in convertToThreeAddress() local
2407 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, in convertToThreeAddress()
2424 if (LV && Src2.isKill()) in convertToThreeAddress()
2434 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddress() local
2438 Src.getReg(), Src.isKill(), Src2, isKill2); in convertToThreeAddress()
2447 LV->replaceKillInstruction(Src2, MI, NewMI); in convertToThreeAddress()
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| H A D | X86ISelLowering.cpp | 17065 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
17069 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
139 Inst.addOperand(Src2); in EmitBinary()
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| H A D | SparcISelLowering.cpp | 2686 SDValue Src2 = Op.getOperand(1); in LowerADDC_ADDE_SUBC_SUBE() local
2687 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2688 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
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| /minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3121 SDValue Src2 = getValue(I.getOperand(1)); in visitShuffleVector() local
3133 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3149 VT, Src1, Src2)); in visitShuffleVector()
3157 VT, Src2, Src1)); in visitShuffleVector()
3165 bool Src2U = Src2.getOpcode() == ISD::UNDEF; in visitShuffleVector()
3171 MOps2[0] = Src2; in visitShuffleVector()
3175 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
3187 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3243 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
3265 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
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| /minix3/external/bsd/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 6318 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); in emitTernaryFPBuiltin() local
6321 return CGF.Builder.CreateCall3(F, Src0, Src1, Src2); in emitTernaryFPBuiltin()
6370 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); in EmitR600BuiltinExpr() local
6376 return Builder.CreateCall4(F, Src0, Src1, Src2, Src3ToBool); in EmitR600BuiltinExpr()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7710 unsigned Src2 = MI->getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
7724 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); in EmitInstrWithCustomInserter()
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