| /minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 784 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
812 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 173 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
189 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
209 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
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| /minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 175 case ISD::SETUGT: in softenSetCCOperands()
1275 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1408 case ISD::SETUGT: in SimplifySetCC()
1431 case ISD::SETUGT: in SimplifySetCC()
1582 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1612 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1618 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1630 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1639 if (Cond == ISD::SETUGT && in SimplifySetCC()
1701 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
[all …]
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| H A D | SelectionDAGDumper.cpp | 313 case ISD::SETUGT: return "setugt"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 909 case ISD::SETUGT: in PromoteSetCCOperands()
2374 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2661 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2701 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
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| H A D | LegalizeDAG.cpp | 1702 case ISD::SETUGT: in LegalizeSetCCCondCode()
3388 Tmp1, Tmp2, ISD::SETUGT); in ExpandNode()
3760 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT; in ExpandNode()
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| H A D | SelectionDAG.cpp | 294 case ISD::SETUGT: in isSignedOp()
344 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE in getSetCCAndOperation()
1827 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); in FoldSetCC()
1876 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSelectCCInfo.td | 30 IntRegs:$fval, SETUGT)),
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| H A D | HexagonISelLowering.cpp | 1134 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal); in HexagonTargetLowering()
1135 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal); in HexagonTargetLowering()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2066 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
2098 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
2118 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2162 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
2170 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
2192 case ISD::SETUGT: in getVCmpInst()
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| H A D | PPCInstrInfo.td | 2660 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2666 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2810 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2855 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
2878 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
2923 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
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| H A D | PPCISelLowering.cpp | 337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
5391 case ISD::SETUGT: in LowerSELECT_CC()
5428 case ISD::SETUGT: in LowerSELECT_CC()
5650 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
290 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
326 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
963 case ISD::SETUGT: in isLegalDSPCondCode()
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| H A D | MipsDSPInstrInfo.td | 1371 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1384 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | AMDGPUInstructions.td | 111 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
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| H A D | AMDGPUISelLowering.cpp | 1110 case ISD::SETUGT: { in CombineFMinMaxLegacy()
1163 case ISD::SETUGT: { in CombineIMinMax()
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| H A D | R600Instructions.td | 800 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
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| H A D | R600ISelLowering.cpp | 55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1223 case ISD::SETUGT: return ARMCC::HI; in IntCCToARMCC()
1248 case ISD::SETUGT: CondCode = ARMCC::HI; break; in FPCCToARMCC()
3287 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
3299 case ISD::SETUGT: in getARMCmp()
3510 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT || in checkVSELConstraints()
3529 CC == ISD::SETUGT) { in checkVSELConstraints()
3638 if (CC == ISD::SETOGT || CC == ISD::SETUGT) in LowerSELECT_CC()
3645 if (CC == ISD::SETOGT || CC == ISD::SETUGT) in LowerSELECT_CC()
4517 case ISD::SETUGT: Swap = true; // Fallthrough in LowerVSETCC()
4549 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; in LowerVSETCC()
[all …]
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| /minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 527 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
879 (setcc node:$lhs, node:$rhs, SETUGT)>;
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 850 case ISD::SETUGT: in EmitCMP()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 981 case ISD::SETUGT: in changeIntCCToAArch64CC()
1032 case ISD::SETUGT: in changeFPCCToAArch64CC()
1076 case ISD::SETUGT: in changeVectorFPCCToAArch64CC()
1162 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getAArch64Cmp()
1179 case ISD::SETUGT: in getAArch64Cmp()
3725 case ISD::SETUGT: in LowerSELECT_CC()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1335 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1359 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3791 case ISD::SETUGT: return X86::COND_A; in TranslateX86CC()
3810 case ISD::SETUGT: in TranslateX86CC()
3832 case ISD::SETUGT: // flipped in TranslateX86CC()
15257 case ISD::SETUGT: SSECC = 6; break; in translateX86FSETCC()
15319 case ISD::SETUGT: SSECC = 6; Unsigned = true; break; in LowerIntVSETCC_AVX512()
15452 case ISD::SETUGT: Opc = X86ISD::PCMPGT; in LowerVSETCC()
23017 case ISD::SETUGT: in matchIntegerMINMAX()
23035 case ISD::SETUGT: in matchIntegerMINMAX()
23162 case ISD::SETUGT: in PerformSELECTCombine()
23201 case ISD::SETUGT: in PerformSELECTCombine()
[all …]
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXVector.td | 970 (setcc node:$lhs, node:$rhs, SETUGT)>;
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