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Searched refs:SELECT_CC (Results 1 – 25 of 39) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/
H A D2010-04-09-NeonSelect.ll2 ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td363 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
366 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
368 "# SELECT_CC PSEUDO!",
1206 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1209 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1212 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1214 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1216 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1218 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1220 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
[all …]
H A DXCoreISelLowering.cpp94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
1556 assert((MI->getOpcode() == XCore::SELECT_CC) && in EmitInstrWithCustomInserter()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h62 SELECT_CC, enumerator
H A DMSP430ISelLowering.cpp115 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
116 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
197 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
987 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSETCC()
1010 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSELECT_CC()
1159 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h341 SELECT_CC, enumerator
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
163 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
590 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1169 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1226 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1250 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1252 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1863 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1871 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PerformDAGCombine()
[all …]
H A DSIISelLowering.cpp98 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in SITargetLowering()
99 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in SITargetLowering()
100 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in SITargetLowering()
101 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in SITargetLowering()
180 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in SITargetLowering()
219 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
H A DAMDGPUISelLowering.cpp293 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
335 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
374 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
384 setTargetDAGCombine(ISD::SELECT_CC); in AMDGPUTargetLowering()
H A DEvergreenInstructions.td583 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp542 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
544 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
H A DLegalizeFloatTypes.cpp102 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
609 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
689 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
876 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1378 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
H A DSelectionDAGDumper.cpp199 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
H A DLegalizeDAG.cpp1209 case ISD::SELECT_CC: in LegalizeOp()
1212 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
1220 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3964 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3970 case ISD::SELECT_CC: { in ExpandNode()
4030 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), in ExpandNode()
4035 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
H A DLegalizeVectorTypes.cpp65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
1715 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
2496 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in WidenVecRes_SELECT_CC()
H A DLegalizeIntegerTypes.cpp72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
551 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteIntRes_SELECT_CC()
841 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1221 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2581 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
H A DDAGCombiner.cpp645 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
1306 case ISD::SELECT_CC: return visitSELECT_CC(N); in visit()
3848 case ISD::SELECT_CC: in visitXOR()
4752 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) || in visitSELECT()
4753 TLI.isOperationLegal(ISD::SELECT_CC, VT)) in visitSELECT()
4754 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, in visitSELECT()
5110 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(), in visitSELECT_CC()
7635 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) { in visitSINT_TO_FP()
7645 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops); in visitSINT_TO_FP()
7658 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops); in visitSINT_TO_FP()
[all …]
H A DLegalizeVectorOps.cpp284 case ISD::SELECT_CC: in LegalizeOp()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1334 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in HexagonTargetLowering()
1335 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in HexagonTargetLowering()
1336 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in HexagonTargetLowering()
1346 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in HexagonTargetLowering()
1347 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in HexagonTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
650 setTargetDAGCombine(ISD::SELECT_CC); in PPCTargetLowering()
6678 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
8020 N->getOpcode() == ISD::SELECT_CC) { in DAGCombineTruncBoolExt()
8063 N->getOperand(0).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
8070 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) && in DAGCombineTruncBoolExt()
8075 N->getOperand(1).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
8115 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3) in DAGCombineTruncBoolExt()
8128 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC || in DAGCombineTruncBoolExt()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in NVPTXTargetLowering()
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in NVPTXTargetLowering()
143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in NVPTXTargetLowering()
144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand); in NVPTXTargetLowering()
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); in NVPTXTargetLowering()
146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in NVPTXTargetLowering()
147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in NVPTXTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
2808 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
332 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
365 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
520 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
632 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); in addTypeForNEON()
1363 if (Sel.getOpcode() != ISD::SELECT_CC) in LowerXOR()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp245 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in MipsTargetLowering()
246 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in MipsTargetLowering()
293 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsTargetLowering()
294 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsTargetLowering()
826 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); in LowerOperation()
H A DMipsSEISelLowering.cpp177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsSETargetLowering()
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in MipsSETargetLowering()
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in MipsSETargetLowering()
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsSETargetLowering()

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