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Searched refs:MachineInstr (Results 1 – 25 of 355) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h50 unsigned isLoadFromStackSlot(const MachineInstr *MI,
58 unsigned isStoreToStackSlot(const MachineInstr *MI,
74 bool analyzeCompare(const MachineInstr *MI,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
103 SmallVectorImpl<MachineInstr*> &NewMIs) const;
105 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106 MachineInstr* MI,
110 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, in foldMemoryOperandImpl()
111 MachineInstr* MI, in foldMemoryOperandImpl()
113 MachineInstr* LoadMI) const override { in foldMemoryOperandImpl()
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H A DHexagonVLIWPacketizer.cpp116 std::vector<MachineInstr*> IgnoreDepMIs;
127 bool ignorePseudoInstruction(MachineInstr *MI,
132 bool isSoloInstruction(MachineInstr *MI) override;
142 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
144 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
148 bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
149 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
153 CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
154 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
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H A DHexagonMachineFunctionInfo.h30 std::vector<MachineInstr*> AllocaAdjustInsts;
34 std::map<const MachineInstr*, unsigned> PacketInfo;
48 void addAllocaAdjustInst(MachineInstr* MI) { in addAllocaAdjustInst()
51 const std::vector<MachineInstr*>& getAllocaAdjustInsts() { in getAllocaAdjustInsts()
58 void setStartPacket(MachineInstr* MI) { in setStartPacket()
61 void setEndPacket(MachineInstr* MI) { in setEndPacket()
64 bool isStartPacket(const MachineInstr* MI) const { in isStartPacket()
68 bool isEndPacket(const MachineInstr* MI) const { in isEndPacket()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetInstrInfo.h73 bool isTriviallyReMaterializable(const MachineInstr *MI,
88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, in isReallyTriviallyReMaterializable()
99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
116 virtual int getSPAdjust(const MachineInstr *MI) const;
124 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
143 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
155 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
164 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, in isStoreToStackSlot()
172 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, in isStoreToStackSlotPostFE()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h48 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
50 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
59 unsigned isLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreToStackSlot(const MachineInstr *MI,
66 bool hasShiftedReg(const MachineInstr *MI) const;
70 bool hasExtendedReg(const MachineInstr *MI) const;
73 bool isGPRZero(const MachineInstr *MI) const;
76 bool isGPRCopy(const MachineInstr *MI) const;
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIInstrInfo.h42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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H A DR600InstrInfo.h29 class MachineInstr; variable
37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
71 bool isTrig(const MachineInstr &MI) const;
85 bool canBeConsideredALU(const MachineInstr *MI) const;
88 bool isTransOnly(const MachineInstr *MI) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
99 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) const;
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H A DAMDGPUInstrInfo.h37 class MachineInstr; variable
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI,
56 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
58 bool hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
62 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
64 bool hasStoreFromStackSlot(const MachineInstr *MI,
68 MachineInstr *
88 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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H A DAMDGPUInstrInfo.cpp40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot()
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, in isStoreFromStackSlot()
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, in isStoreFromStackSlotPostFE()
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, in hasStoreFromStackSlot()
82 MachineInstr *
156 MachineInstr *
158 MachineInstr *MI, in foldMemoryOperandImpl()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.h122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { in isLeaMem()
134 inline static bool isMem(const MachineInstr *MI, unsigned Op) { in isMem()
184 bool isCoalescableExtInstr(const MachineInstr &MI,
188 unsigned isLoadFromStackSlot(const MachineInstr *MI,
193 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
196 unsigned isStoreToStackSlot(const MachineInstr *MI,
201 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
204 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
208 const MachineInstr *Orig,
219 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h56 const MachineInstr &MI, unsigned DefIdx,
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
97 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
127 bool isPredicated(const MachineInstr *MI) const override;
129 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
135 bool PredicateInstruction(MachineInstr *MI,
141 bool DefinesPredicate(MachineInstr *MI,
144 bool isPredicable(MachineInstr *MI) const override;
148 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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H A DMLxExpansionPass.cpp58 MachineInstr* LastMIs[4];
59 SmallPtrSet<MachineInstr*, 4> IgnoreStall;
62 void pushStack(MachineInstr *MI);
63 MachineInstr *getAccDefMI(MachineInstr *MI) const;
64 unsigned getDefReg(MachineInstr *MI) const;
65 bool hasLoopHazard(MachineInstr *MI) const;
66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
67 bool FindMLxHazard(MachineInstr *MI);
68 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
81 void MLxExpansion::pushStack(MachineInstr *MI) { in pushStack()
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H A DA15SDOptimizer.cpp61 bool runOnInstruction(MachineInstr *MI);
101 bool hasPartialWrite(MachineInstr *MI);
102 SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
109 MachineInstr *elideCopies(MachineInstr *MI);
110 void elideCopiesAndPHIs(MachineInstr *MI,
111 SmallVectorImpl<MachineInstr*> &Outs);
116 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
117 unsigned optimizeSDPattern(MachineInstr *MI);
123 void eraseInstrWithNoUses(MachineInstr *MI);
128 std::map<MachineInstr*, unsigned> Replacements;
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveVariables.h89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr *MI) { in removeKill()
95 std::vector<MachineInstr*>::iterator in removeKill()
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
137 std::vector<MachineInstr *> PhysRegDef;
142 std::vector<MachineInstr *> PhysRegUse;
148 DenseMap<MachineInstr*, unsigned> DistanceMap;
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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H A DMachineInstrBundle.h46 inline MachineInstr *getBundleStart(MachineInstr *MI) { in getBundleStart()
53 inline const MachineInstr *getBundleStart(const MachineInstr *MI) { in getBundleStart()
62 getBundleEnd(MachineInstr *MI) { in getBundleEnd()
71 getBundleEnd(const MachineInstr *MI) { in getBundleEnd()
96 MachineInstr::mop_iterator OpI, OpE;
117 explicit MachineOperandIteratorBase(MachineInstr *MI, bool WholeBundle) { in MachineOperandIteratorBase()
199 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr);
214 MIOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, false) {} in MIOperands()
223 ConstMIOperands(const MachineInstr *MI) in ConstMIOperands()
224 : MachineOperandIteratorBase(const_cast<MachineInstr*>(MI), false) {} in ConstMIOperands()
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H A DMachineBasicBlock.h34 struct ilist_traits<MachineInstr> : public ilist_default_traits<MachineInstr> {
36 mutable ilist_half_node<MachineInstr> Sentinel;
43 MachineInstr *createSentinel() const {
44 return static_cast<MachineInstr*>(&Sentinel);
46 void destroySentinel(MachineInstr *) const {}
48 MachineInstr *provideInitialHead() const { return createSentinel(); }
49 MachineInstr *ensureHead(MachineInstr*) const { return createSentinel(); }
50 static void noteHead(MachineInstr*, MachineInstr*) {}
52 void addNodeToList(MachineInstr* N);
53 void removeNodeFromList(MachineInstr* N);
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H A DDFAPacketizer.h36 class MachineInstr; variable
76 bool canReserveResources(llvm::MachineInstr *MI);
80 void reserveResources(llvm::MachineInstr *MI);
101 std::vector<MachineInstr*> CurrentPacketMIs;
106 std::map<MachineInstr*, SUnit*> MIToSUnit;
122 virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { in addToPacket()
130 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
138 virtual bool ignorePseudoInstruction(MachineInstr *I, in ignorePseudoInstruction()
145 virtual bool isSoloInstruction(MachineInstr *MI) { in isSoloInstruction()
H A DStackMaps.h45 const MachineInstr *MI;
49 explicit PatchPointOpers(const MachineInstr *MI);
99 explicit StatepointOpers(const MachineInstr *MI): in StatepointOpers()
127 const MachineInstr *MI;
176 void recordStackMap(const MachineInstr &MI);
179 void recordPatchPoint(const MachineInstr &MI);
182 void recordStatepoint(const MachineInstr &MI);
215 MachineInstr::const_mop_iterator
216 parseOperand(MachineInstr::const_mop_iterator MOI,
217 MachineInstr::const_mop_iterator MOE,
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
99 const MachineInstr *DefMI, unsigned DefIdx,
100 const MachineInstr *UseMI,
110 const MachineInstr *DefMI, in hasLowDefLatency()
118 bool isCoalescableExtInstr(const MachineInstr &MI,
121 unsigned isLoadFromStackSlot(const MachineInstr *MI,
123 unsigned isStoreToStackSlot(const MachineInstr *MI,
128 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
130 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h120 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
122 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
124 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
126 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
137 unsigned isLoadFromStackSlot(const MachineInstr *MI,
139 unsigned isStoreToStackSlot(const MachineInstr *MI,
141 bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
152 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
154 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
157 bool isPredicable(MachineInstr *MI) const override;
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H A DSystemZElimCompare.cpp77 Reference getRegReferences(MachineInstr *MI, unsigned Reg);
78 bool convertToBRCT(MachineInstr *MI, MachineInstr *Compare,
79 SmallVectorImpl<MachineInstr *> &CCUsers);
80 bool convertToLoadAndTest(MachineInstr *MI);
81 bool adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare,
82 SmallVectorImpl<MachineInstr *> &CCUsers);
83 bool optimizeCompareZero(MachineInstr *Compare,
84 SmallVectorImpl<MachineInstr *> &CCUsers);
85 bool fuseCompareAndBranch(MachineInstr *Compare,
86 SmallVectorImpl<MachineInstr *> &CCUsers);
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h27 class MachineInstr; variable
36 void EmitInstrWithMacroNoAT(const MachineInstr *MI);
41 const MachineInstr *MI);
47 const MachineInstr *MI);
120 void EmitInstruction(const MachineInstr *MI) override;
129 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
132 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
135 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
136 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
137 void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
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H A DMipsSEISelLowering.h43 EmitInstrWithCustomInserter(MachineInstr *MI,
80 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
82 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
86 MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
89 MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
92 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
95 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
98 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
103 MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
106 MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
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/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DMachineCombiner.cpp63 MachineInstr *getOperandDef(const MachineOperand &MO);
64 unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
67 unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
70 preservesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
72 SmallVectorImpl<MachineInstr *> &InsInstrs,
76 SmallVectorImpl<MachineInstr *> &InsInstrs,
77 SmallVectorImpl<MachineInstr *> &DelInstrs);
78 void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
101 MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) { in getOperandDef()
102 MachineInstr *DefInstr = nullptr; in getOperandDef()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
53 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 bool PrintAsmMemoryOperand(const MachineInstr *MI,
59 void EmitInstruction(const MachineInstr *MI) override;
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, in printOperand()
105 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, in printSrcMemOperand()
127 bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, in PrintAsmOperand()
138 bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, in PrintAsmMemoryOperand()
150 void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { in EmitInstruction()

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