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Searched refs:GPR32 (Results 1 – 20 of 20) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
47 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
62 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
75 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
77 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
90 def : Pat<(relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
92 (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
127 def : Pat<(releasing_store<atomic_store_8> GPR64sp:$ptr, GPR32:$val),
128 (STLRB GPR32:$val, GPR64sp:$ptr)>;
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H A DAArch64InstrInfo.td402 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
404 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
406 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
425 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
426 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
428 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
429 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
431 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
432 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
452 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
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H A DAArch64InstrFormats.td180 def GPR32as64 : RegisterOperand<GPR32> {
566 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
588 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
669 let MIOperandInfo = (ops GPR32, arith_extend);
675 let MIOperandInfo = (ops GPR32, arith_extend64);
1047 def W : BaseCmpBranch<GPR32, op, asm, node> {
1118 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1190 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1200 : BaseOneOperandData<opc, GPR32, asm, node> {
1244 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
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H A DAArch64RegisterInfo.td124 // GPR register classes with the intersections of GPR32/GPR32sp and
136 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
137 let AltOrders = [(rotl GPR32, 8)];
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/
H A Ddivrem.ll3 …machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=GPR32-TRAP
10 …o-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NOCH…
19 ; GPR32 - GPR based multiply/divide on 32-bit targets
20 ; GPR64 - Same as GPR32 but only for 64-bit targets
23 ; GPR32-TRAP - Same as TRAP and GPR32 combined
40 ; GPR32: div $2, $4, $5
41 ; GPR32-TRAP: teq $5, $zero, 7
67 ; GPR32: mod $2, $4, $5
68 ; GPR32-TRAP: teq $5, $zero, 7
94 ; GPR32: divu $2, $4, $5
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCondMov.td202 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
205 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
207 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
209 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
213 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
215 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
219 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
221 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
226 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
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H A DMipsInstrInfo.td1068 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1069 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1070 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1071 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1072 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1073 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1074 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1075 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1076 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1077 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
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H A DMicroMipsInstrInfo.td93 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
101 let MIOperandInfo = (ops GPR32, simm12);
117 let MIOperandInfo = (ops GPR32, uimm8);
797 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
798 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
799 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
800 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
804 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
805 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
809 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
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H A DMips64InstrInfo.td254 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
256 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
432 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
433 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
434 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
H A DMipsDSPInstrInfo.td1272 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1283 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1284 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1285 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1286 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1293 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1295 (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1388 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1389 (Instr ACC64DSP:$ac, GPR32:$rs)>;
H A DMipsRegisterInfo.td288 def GPR32 : GPR32Class<[i32]>;
515 def GPR32Opnd : RegisterOperand<GPR32> {
H A DMipsMSAInstrInfo.td3729 MipsPseudo<(outs GPR32:$dst),
3731 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3762 GPR32), (i32 24))>;
3767 GPR32), (i32 16))>;
3772 GPR32)>;
3783 GPR32), (i32 24))>;
3788 GPR32), (i32 16))>;
3793 GPR32)>;
H A DMips16InstrInfo.td290 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
298 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll10 …ps32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-M…
11 …ps32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC…
12 …ps32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC…
102 ; GPR32-DAG: ori $3, $[[T0]], 1
103 ; GPR32-DAG: addiu $2, $zero, 0
117 ; GPR32-DAG: ori $2, $[[T0]], 1
118 ; GPR32-DAG: addiu $3, $zero, 0
131 ; GPR32-DAG: lui $[[T0:[0-9]+]], 1
132 ; GPR32-DAG: lui $[[T1:[0-9]+]], 2
133 ; GPR32-DAG: ori $2, $[[T0]], 1
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td54 class GPR32<bits<16> num, string n> : SystemZReg<n> {
59 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
74 def R#I#L : GPR32<I, "r"#I>;
75 def R#I#H : GPR32<I, "r"#I>;
76 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
H A DSystemZFrameLowering.cpp114 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR() local
115 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR()
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/
H A Darm64-dead-register-def-bug.ll6 ; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
H A Ddp2.ll139 ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
H A Dbitfield.ll172 ; making sure that a 64-bit "(sext_inreg (anyext GPR32), i1)" uses the 64-bit
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/msa/
H A D3r_splat.ll88 ; GPR32.