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Searched refs:FP_TO_SINT (Results 1 – 25 of 31) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp264 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
266 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
268 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
282 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
284 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
286 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
300 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
302 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
304 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
306 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp108 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
113 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
532 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
565 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
876 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
3915 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
3930 case ISD::FP_TO_SINT: in LowerFP_TO_INT()
6118 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6155 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6264 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp347 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
348 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
349 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
355 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
356 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
357 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
363 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
364 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
369 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
370 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
188 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
189 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
523 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
647 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); in addTypeForNEON()
1576 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
1972 case ISD::FP_TO_SINT: in LowerOperation()
8717 case ISD::FP_TO_SINT: in ReplaceNodeResults()
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A Davx-fp2int.ll3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/R600/
H A Dfcmp.ll19 ; SET* + FP_TO_SINT
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
H A DX86TargetTransformInfo.cpp737 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, in getCastInstrCost()
738 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, in getCastInstrCost()
H A DX86ISelLowering.cpp364 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); in resetOperationActions()
369 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); in resetOperationActions()
370 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); in resetOperationActions()
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); in resetOperationActions()
375 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in resetOperationActions()
377 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); in resetOperationActions()
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in resetOperationActions()
874 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in resetOperationActions()
1076 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in resetOperationActions()
1223 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote); in resetOperationActions()
[all …]
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h420 FP_TO_SINT, enumerator
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp290 case ISD::FP_TO_SINT: in LegalizeOp()
371 case ISD::FP_TO_SINT: in Promote()
373 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); in Promote()
457 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
458 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp687 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break; in SoftenFloatOperand()
1376 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1483 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1507 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1513 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
H A DSelectionDAGDumper.cpp238 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeVectorTypes.cpp88 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
430 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
630 case ISD::FP_TO_SINT: in SplitVectorResult()
1311 case ISD::FP_TO_SINT: in SplitVectorOperand()
1765 case ISD::FP_TO_SINT: in WidenVectorResult()
2607 case ISD::FP_TO_SINT: in WidenVectorOperand()
H A DLegalizeDAG.cpp2653 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2654 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3152 case ISD::FP_TO_SINT: in ExpandNode()
3168 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
3169 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
4168 case ISD::FP_TO_SINT: in PromoteNode()
4170 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
H A DLegalizeIntegerTypes.cpp100 case ISD::FP_TO_SINT: in PromoteIntegerResult()
392 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
393 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
1240 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1146 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1151 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1156 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1161 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in HexagonTargetLowering()
1166 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); in HexagonTargetLowering()
1178 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in HexagonTargetLowering()
1233 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); in HexagonTargetLowering()
1236 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); in HexagonTargetLowering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
5456 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : in LowerFP_TO_INTForReuse()
5462 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTForReuse()
5464 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ : in LowerFP_TO_INTForReuse()
5472 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
161 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
868 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1857 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp291 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
309 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
607 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
1537 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2093 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
2798 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3191 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3197 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
841 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2253 if (Val.getOpcode() != ISD::FP_TO_SINT) in lowerFP_TO_SINT_STORE()
H A DMipsSEISelLowering.cpp279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); in addMSAIntType()
1890 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/minix3/external/bsd/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst1394 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1398 code, an ``FP_TO_SINT`` opcode will call the ``LowerFP_TO_SINT`` method:
1404 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1419 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()

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