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/llvm-project/llvm/test/MC/ARM/
H A Dvstrldr_sys.s70 vldr fpscr, [r0] label
78 vldr fpscr_nzcvqc, [r9, #-24] label
86 vldr fpscr_nzcvqc, [r9, #-24]! label
94 vldr fpscr_nzcvqc, [r9], #-24 label
102 vldr fpscr_nzcvqc, [sp], #-52 label
156 vldr fpcxts, [r12, #508] label
164 vldr fpcxts, [r12, #508]! label
172 vldr fpcxts, [r12], #508 label
180 vldr fpcxts, [sp], #-24 label
236 vldr fpcxtns, [r0] label
[all …]
H A Dpcrel-vldr-same-section.s19 vldr s0, foo @ arm_pcrel_10 / t2_pcrel_10
20 vldr d0, foo @ arm_pcrel_10 / t2_pcrel_10 define
21 vldr.16 s0, foo @ arm_pcrel_9 / t2_pcrel_9
22 vldr s0, bar-8
23 vldr d0, bar-8 define
24 vldr.16 s0, bar-8
25 vldr s0, baz
26 vldr d0, baz define
27 vldr.16 s0, baz
28 vldr s0, label-8
[all …]
H A Dsimple-fp-encoding.s244 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
245 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
246 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
248 vldr.64 d17, [r0]
249 vldr.i32 s0, [lr]
250 vldr.d d0, [lr]
252 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
253 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
254 vldr.64 d1, [r2, #32]
255 vldr.f64 d1, [r2, #-32]
[all …]
/llvm-project/llvm/test/tools/llvm-objdump/ELF/ARM/
H A Dliteral-vldr-thumb2.s18 vldr d0, foo define
19 vldr s0, bar
20 @ CHECK: 4: vldr d0, [pc, #-8] @ 0x0 <foo>
21 @ CHECK-NEXT: 8: vldr s0, [pc, #56] @ 0x44 <bar>
25 vldr d0, foo define
26 vldr s0, bar
27 @ CHECK: e: vldr d0, [pc, #-16] @ 0x0 <foo>
28 @ CHECK-NEXT: 12: vldr s0, [pc, #48] @ 0x44 <bar>
31 vldr d0, [r1, #8] define
32 @ CHECK: 16: vldr d0, [r1, #8]{{$}}
[all …]
H A Dliteral-vldr-arm.s18 vldr d0, foo define
19 vldr s0, bar
20 @ CHECK-NEXT: 4: vldr d0, [pc, #-12] @ 0x0 <foo>
21 @ CHECK-NEXT: 8: vldr s0, [pc, #20] @ 0x24 <bar>
25 vldr d0, [r1, #8] define
26 @ CHECK-NEXT: c: vldr d0, [r1, #8]{{$}}
29 vldr.16 s0, foo
30 vldr.16 s0, foo2
31 vldr.16 s1, bar
32 vldr.16 s1, bar2
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dfp16-fusedMAC.ll10 ; CHECK-NEXT: vldr.16 s0, [r1]
11 ; CHECK-NEXT: vldr.16 s2, [r0]
12 ; CHECK-NEXT: vldr.16 s4, [r2]
19 ; DONT-FUSE-NEXT: vldr.16 s0, [r1]
20 ; DONT-FUSE-NEXT: vldr.16 s2, [r0]
22 ; DONT-FUSE-NEXT: vldr.16 s2, [r2]
39 ; CHECK-NEXT: vldr.16 s0, [r2]
40 ; CHECK-NEXT: vldr.16 s2, [r1]
41 ; CHECK-NEXT: vldr.16 s4, [r0]
48 ; DONT-FUSE-NEXT: vldr.16 s0, [r2]
[all …]
H A Dvsel-fp16.ll9 ; CHECK-NEXT: vldr.16 s0, [r2]
10 ; CHECK-NEXT: vldr.16 s2, [r3]
28 ; CHECK-NEXT: vldr.16 s0, [r2]
29 ; CHECK-NEXT: vldr.16 s2, [r3]
47 ; CHECK-NEXT: vldr.16 s0, [r2]
48 ; CHECK-NEXT: vldr.16 s2, [r3]
66 ; CHECK-NEXT: vldr.16 s0, [r2]
67 ; CHECK-NEXT: vldr.16 s2, [r3]
85 ; CHECK-NEXT: vldr.16 s0, [r2]
86 ; CHECK-NEXT: vldr.16 s2, [r3]
[all …]
H A Dsaxpy10-a9.ll12 ; CHECK: vldr
13 ; CHECK: vldr
14 ; CHECK: vldr
15 ; CHECK: vldr
16 ; CHECK: vldr
17 ; CHECK-NEXT: vldr
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vldr
26 ; CHECK-NEXT: vldr
29 ; CHECK-NEXT: vldr
[all …]
H A Dconstantfp.ll45 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
48 ; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
53 ; CHECK-XO-FLOAT-NOT: vldr
62 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
65 ; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
70 ; CHECK-XO-FLOAT-NOT: vldr
89 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
92 ; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
97 ; CHECK-XO-DOUBLE-NOT: vldr
102 ; CHECK-XO-DOUBLE-NOT: vldr
[all …]
H A Dfp16-fullfp16.ll6 ; CHECK: vldr.16 s0, [r1]
7 ; CHECK-NEXT: vldr.16 s2, [r0]
20 ; CHECK: vldr.16 s0, [r1]
21 ; CHECK-NEXT: vldr.16 s2, [r0]
34 ; CHECK: vldr.16 s0, [r1]
35 ; CHECK-NEXT: vldr.16 s2, [r0]
48 ; CHECK: vldr.16 s0, [r1]
49 ; CHECK-NEXT: vldr.16 s2, [r0]
64 ; CHECK-NEXT: vldr.16 s0, [r0]
65 ; CHECK-NEXT: vldr.16 s2, [r1]
[all …]
H A Dvaba.ll7 ; CHECK-NEXT: vldr d16, [r2]
8 ; CHECK-NEXT: vldr d17, [r1]
9 ; CHECK-NEXT: vldr d0, [r0]
23 ; CHECK-NEXT: vldr d16, [r2]
24 ; CHECK-NEXT: vldr d17, [r1]
25 ; CHECK-NEXT: vldr d0, [r0]
39 ; CHECK-NEXT: vldr d16, [r2]
40 ; CHECK-NEXT: vldr d17, [r1]
41 ; CHECK-NEXT: vldr d0, [r0]
55 ; CHECK-NEXT: vldr d16, [r2]
[all …]
H A Dvcgt.ll8 ; ALLOC-NEXT: vldr d16, [r1]
9 ; ALLOC-NEXT: vldr d17, [r0]
16 ; BASIC-NEXT: vldr d17, [r1]
17 ; BASIC-NEXT: vldr d16, [r0]
31 ; ALLOC-NEXT: vldr d16, [r1]
32 ; ALLOC-NEXT: vldr d17, [r0]
39 ; BASIC-NEXT: vldr d17, [r1]
40 ; BASIC-NEXT: vldr d16, [r0]
54 ; ALLOC-NEXT: vldr d16, [r1]
55 ; ALLOC-NEXT: vldr d17, [r0]
[all …]
H A Dvabd.ll7 ; CHECK-NEXT: vldr d16, [r1]
8 ; CHECK-NEXT: vldr d17, [r0]
20 ; CHECK-NEXT: vldr d16, [r1]
21 ; CHECK-NEXT: vldr d17, [r0]
33 ; CHECK-NEXT: vldr d16, [r1]
34 ; CHECK-NEXT: vldr d17, [r0]
46 ; CHECK-NEXT: vldr d16, [r1]
47 ; CHECK-NEXT: vldr d17, [r0]
59 ; CHECK-NEXT: vldr d16, [r1]
60 ; CHECK-NEXT: vldr d17, [r0]
[all …]
H A Dvbits.ll7 ; CHECK-NEXT: vldr d16, [r1]
8 ; CHECK-NEXT: vldr d17, [r0]
21 ; CHECK-NEXT: vldr d16, [r1]
22 ; CHECK-NEXT: vldr d17, [r0]
35 ; CHECK-NEXT: vldr d16, [r1]
36 ; CHECK-NEXT: vldr d17, [r0]
49 ; CHECK-NEXT: vldr d16, [r1]
50 ; CHECK-NEXT: vldr d17, [r0]
123 ; CHECK-NEXT: vldr d16, [r1]
124 ; CHECK-NEXT: vldr d17, [r0]
[all …]
H A Dvcombine.ll6 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
22 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
39 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
56 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
72 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
[all …]
H A Dfp16-vminmaxnm.ll173 ; CHECK: vldr.16 s2, .LCPI{{.*}}
186 ; CHECK: vldr.16 s2, .LCPI{{.*}}
189 ; CHECK: vldr.16 s2, .LCPI{{.*}}
205 ; CHECK: vldr.16 s2, .LCPI{{.*}}
218 ; CHECK: vldr.16 s2, .LCPI{{.*}}
221 ; CHECK: vldr.16 s2, .LCPI{{.*}}
234 ; CHECK: vldr.16 s2, .LCPI{{.*}}
237 ; CHECK: vldr.16 s2, .LCPI{{.*}}
253 ; CHECK: vldr.16 s2, .LCPI{{.*}}
266 ; CHECK: vldr.16 s2, .LCPI{{.*}}
[all …]
H A Dcmse-clear-float-hard2.ll41 ; CHECK-V8-LE-NEXT: vldr d4, [sp, #32]
42 ; CHECK-V8-LE-NEXT: vldr d5, [sp, #40]
43 ; CHECK-V8-LE-NEXT: vldr d6, [sp, #48]
44 ; CHECK-V8-LE-NEXT: vldr s14, [sp, #56]
81 ; CHECK-V8-BE-NEXT: vldr s8, [sp, #32]
82 ; CHECK-V8-BE-NEXT: vldr s9, [sp, #36]
83 ; CHECK-V8-BE-NEXT: vldr s10, [sp, #40]
84 ; CHECK-V8-BE-NEXT: vldr s11, [sp, #44]
85 ; CHECK-V8-BE-NEXT: vldr s12, [sp, #48]
86 ; CHECK-V8-BE-NEXT: vldr s13, [sp, #52]
[all …]
H A Dvcge.ll7 ; CHECK-NEXT: vldr d16, [r1]
8 ; CHECK-NEXT: vldr d17, [r0]
22 ; CHECK-NEXT: vldr d16, [r1]
23 ; CHECK-NEXT: vldr d17, [r0]
37 ; CHECK-NEXT: vldr d16, [r1]
38 ; CHECK-NEXT: vldr d17, [r0]
52 ; CHECK-NEXT: vldr d16, [r1]
53 ; CHECK-NEXT: vldr d17, [r0]
67 ; CHECK-NEXT: vldr d16, [r1]
68 ; CHECK-NEXT: vldr d17, [r0]
[all …]
H A Dvector-store.ll188 ; CHECK-LE-NEXT: vldr d17, [sp]
196 ; CHECK-BE-NEXT: vldr d17, [sp]
210 ; CHECK-LE-NEXT: vldr d17, [sp]
219 ; CHECK-BE-NEXT: vldr d17, [sp]
236 ; CHECK-LE-NEXT: vldr d17, [sp]
244 ; CHECK-BE-NEXT: vldr d17, [sp]
258 ; CHECK-LE-NEXT: vldr d17, [sp]
267 ; CHECK-BE-NEXT: vldr d17, [sp]
284 ; CHECK-LE-NEXT: vldr d17, [sp]
292 ; CHECK-BE-NEXT: vldr d17, [sp]
[all …]
H A Dvldm-sched-a9.ll12 ; elements and then a sequence of vldr are used:
13 ; vldr d15, [r1, #104]
14 ; vldr d13, [r2, #96]
15 ; vldr d9, [r1, #120]
16 ; vldr d11, [r2, #112]
17 ; vldr d14, [r1, #96]
18 ; vldr d12, [r2, #88]
19 ; vldr d8, [r1, #112]
20 ; vldr d10, [r2, #104]
24 ; vldr d16, [r1, #16]
[all …]
H A Dvceq.ll7 ; CHECK-NEXT: vldr d16, [r1]
8 ; CHECK-NEXT: vldr d17, [r0]
22 ; CHECK-NEXT: vldr d16, [r1]
23 ; CHECK-NEXT: vldr d17, [r0]
37 ; CHECK-NEXT: vldr d16, [r1]
38 ; CHECK-NEXT: vldr d17, [r0]
52 ; CHECK-NEXT: vldr d16, [r1]
53 ; CHECK-NEXT: vldr d17, [r0]
131 ; CHECK-NEXT: vldr d16, [r0]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dvstrldr_sys.txt53 # CHECK-NOSEC: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
54 # CHECK-NOMVE: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
55 # CHECK-NOVFP: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
56 # CHECK: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
59 # CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
60 # CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
61 # CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
62 # CHECK: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
65 # CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
66 # CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
[all …]
/llvm-project/libc/AOR_v20.02/string/arm/
H A Dmemcpy.S88 vldr \vreg, [src, #\base]
90 vldr d0, [src, #\base + 8] define
92 vldr d1, [src, #\base + 16] define
94 vldr d2, [src, #\base + 24] define
96 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
98 vldr d0, [src, #\base + 40] define
100 vldr d1, [src, #\base + 48] define
102 vldr d2, [src, #\base + 56] define
107 vldr \vreg, [src, #\base]
109 vldr d0, [src, #\base + 8] define
[all …]
/llvm-project/llvm/test/Analysis/CostModel/ARM/
H A Dadd-cast-vect.ll34 ; ASM: vldr
36 ; ASM: vldr
51 ; ASM: vldr
53 ; ASM: vldr
68 ; ASM: vldr
70 ; ASM: vldr
85 ; ASM: vldr
87 ; ASM: vldr
/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dvldr.ll13 …%1 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %0…
20 declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32)
31 …%1 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> …
38 declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32)
53 …%3 = tail call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v…
63 declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x…

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