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Searched refs:v_trunc_f16_dpp (Results 1 – 21 of 21) sorted by relevance

/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx10_asm_dpp8.s147 v_trunc_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
399 v_trunc_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
H A Dgfx8_asm_vop1.s12747 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
12750 v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
12753 v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
12756 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
12759 v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
12762 v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 label
12765 v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 label
12768 v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 label
12771 v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
12774 v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
[all …]
H A Dgfx10_asm_dpp16.s216 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
516 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
H A Dgfx9_asm_vop1.s15063 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
15066 v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
15069 v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
15072 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
15075 v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
15078 v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 label
15081 v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 label
15084 v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 label
15087 v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
15090 v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
[all …]
H A Dgfx10_asm_vop1.s14653 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14656 v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14659 v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
14662 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
14665 v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
14668 v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 label
14671 v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
14674 v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
14677 v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
14680 v_trunc_f16_dpp v label
14644 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 global() label
14647 v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 global() label
14650 v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 global() label
14683 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 global() label
14686 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 global() label
14689 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 global() label
14692 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 global() label
14695 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 global() label
14698 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf global() label
14701 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 global() label
14704 v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 global() label
14707 v_trunc_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0 global() label
14710 v_trunc_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0 global() label
14713 v_trunc_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0 global() label
14716 v_trunc_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0 global() label
[all...]
H A Dgfx7_unsupported.s2512 v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 label
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx10_vop1_dpp8.txt145 # GFX10: v_trunc_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
307 # GFX10: v_trunc_f16_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0xba,0x0a,0x7e,0x01,0x88,0xc6,0xfa]
H A Dgfx10_vop1_dpp16.txt3974 # GFX10: v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xba,0xfe,0x7f,0x01,0xe4,0x00,0x00]
3977 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x00]
3980 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00]
3983 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x01]
3986 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x03]
3989 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
3992 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x10]
3995 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x30]
3998 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
4001 # GFX10: v_trunc_f16_dpp v
[all...]
H A Dgfx9_vop1_dpp.txt3720 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
3723 # CHECK: v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3726 # CHECK: v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3729 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
3732 # CHECK: v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
3735 # CHECK: v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0…
3738 # CHECK: v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a…
3741 # CHECK: v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a…
3744 # CHECK: v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
3747 # CHECK: v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
[all …]
H A Dgfx8_vop1_dpp.txt3720 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
3723 # CHECK: v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3726 # CHECK: v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,…
3729 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x…
3732 # CHECK: v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
3735 # CHECK: v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0…
3738 # CHECK: v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a…
3741 # CHECK: v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a…
3744 # CHECK: v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
3747 # CHECK: v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0…
[all …]
H A Dgfx12_dasm_vop1_dpp8.txt609 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
610 # GFX12-FAKE16: v_trunc_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
613 # GFX12-REAL16: v_trunc_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
614 # GFX12-FAKE16: v_trunc_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
617 # GFX12-REAL16: v_trunc_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
621 # GFX12-REAL16: v_trunc_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
H A Dgfx12_dasm_vop1_dpp16.txt3094 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
3095 # GFX12-FAKE16: v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
3098 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
3099 # GFX12-FAKE16: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
3102 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
3103 # GFX12-FAKE16: v_trunc_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
3106 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
3107 # GFX12-FAKE16: v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
3110 # GFX12-REAL16: v_trunc_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0xff]
3111 # GFX12-FAKE16: v_trunc_f16_dpp v
[all...]
H A Dgfx11_dasm_vop1_dpp16.txt2986 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
2987 # GFX11-FAKE16: v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0xff]
2990 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
2991 # GFX11-FAKE16: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xff]
2994 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
2995 # GFX11-FAKE16: v_trunc_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0xff]
2998 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
2999 # GFX11-FAKE16: v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0xff]
3002 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0xff]
3003 # GFX11-FAKE16: v_trunc_f16_dpp v
[all...]
H A Dgfx11_dasm_vop1_dpp8.txt637 # GFX11-REAL16: v_trunc_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
638 # GFX11-FAKE16: v_trunc_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7e,0x01,0x77,0x39,0x05]
641 # GFX11-REAL16: v_trunc_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
642 # GFX11-FAKE16: v_trunc_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7e,0x7f,0x00,0x00,0x00]
645 # GFX11-REAL16: v_trunc_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0xfe,0x7e,0x7f,0x77,0x39,0x05]
646 # GFX11-FAKE16: v_trunc_f16_dpp v127, v127 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0xfe,0x7e,0x7f,0x77,0x39,0x05]
649 # GFX11-REAL16: v_trunc_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xba,0x0a,0x7f,0x81,0x77,0x39,0x05]
653 # GFX11-REAL16: v_trunc_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xba,0xfe,0x7f,0xff,0x00,0x00,0x00]
/llvm-project/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX1030.rst139 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgp…
247 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:…
H A DAMDGPUAsmGFX10.rst136 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_…
243 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`v…
H A DAMDGPUAsmGFX8.rst859 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vsrc<amdgpu_s…
H A DAMDGPUAsmGFX11.rst1223 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx11_vdst_d180f4>`, :ref:`vsrc<amdgpu_…
1298 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx11_vdst_d180f4>`, :ref:`vsrc<amdgpu_…
H A DAMDGPUAsmGFX9.rst1047 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vsrc<am…
H A DAMDGPUAsmGFX90a.rst956 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`vsrc<…
H A DAMDGPUAsmGFX940.rst952 …v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`vsrc<…